SPRUJ69 December   2022 AM68 , AM68A , TDA4AL-Q1 , TDA4VE-Q1 , TDA4VL-Q1

 

  1.   Trademarks
  2. 1Introduction
    1. 1.1 Inside the Box
    2. 1.2 Key Features
    3. 1.3 Thermal Compliance
    4. 1.4 Reach Compliance
    5. 1.5 EMC, EMI, and ESD Compliance
  3. 2User Interfaces
    1. 2.1 Power Inputs
    2. 2.2 Power Input [J7_CP] with LED for Status [LD2_CP][LD3_CP]
      1. 2.2.1 Power Control [SW2_CP] with LED for Status [LD5_CP] [LD6_CP] [LD7_CP]
      2. 2.2.2 Power Budget Considerations
    3. 2.3 User Inputs
      1. 2.3.1 Board Configuration Settings [SW3_CP] [SW13_CP] [SW3_SOM]
      2. 2.3.2 Boot Configuration Settings [SW9_CP] [SW8_CP]
      3. 2.3.3 Reset Pushbuttons [SW7_CP] [SW6_CP] [SW5_CP] [SW4_CP]
      4. 2.3.4 User Pushbuttons [SW2] [SW11] [SW10] [SW1] [SW12] with User LED Indication [LD9] [LD8]
    4. 2.4 Standard Interfaces
      1. 2.4.1 Uart-Over-USB [J43_CP] [J44_CP] with LED for Status [LD10_CP] [LD11_CP]
      2. 2.4.2 Gigabit Ethernet [J35_CP] with Integrated LEDs for Status
      3. 2.4.3 USB3.1 Gen1 Interface [J5_CP]
      4. 2.4.4 USB2.0 Interface [J6_CP]
      5. 2.4.5 PCIe Card Slot [J8_CP]
      6. 2.4.6 Display Port Interfaces [J36_CP] [J37_CP]
      7. 2.4.7 MicroSD Card Cage [J49_CP]
      8. 2.4.8 Stereo Audio Interface [LINE-IN J38_CP, LINE-OUT J41B_CP, J40B_CP]
    5. 2.5 Expansion Interfaces
      1. 2.5.1 Heatsink [ACC3_SOM] with Fan Header [J15_CP]
      2. 2.5.2 CAN-FD Connectors
      3. 2.5.3 Camera Interfaces [J52_CP]
      4. 2.5.4 Automation and Control Connector [J50_CP]
      5. 2.5.5 ADC [J23_CP]
      6. 2.5.6 CSI-TX [J10_SOM]
      7. 2.5.7 Accessory Power Connector [J42_CP]
  4. 3Circuit Details
    1. 3.1 Top Level Diagram
    2. 3.2 Interface Mapping
    3. 3.3 I2C Address Mapping
    4. 3.4 GPIO Mapping
      1. 3.4.1 Power Monitoring
      2. 3.4.2 Shared Interfaces / Signal Muxing
      3. 3.4.3 Power Delivery Network (PDN)
      4. 3.4.4 Identification EEPROM
  5. 4Revision History

3.4 GPIO Mapping

The General Purpose IOs (GPIO) of the EVM are broken into two major groups, IO connected to J7AEP or connected to I2C-based Expander. They are separated into Table 3-3 and Table 3-4.

Table 3-3 GPIO Mapping for Processor IO
GPIO Number Function Input/Output Remarks
WKUP_GPIO0_0 MCU CAN0 Enable Output

‘0’ – CAN Enable

‘1’ – CAN is disabled (Default)
WKUP_GPIO0_1 Boot EEPROM Write protect Output

‘0’ – Memory is NOT Write-Protected

‘1’ – Memory is Write-Protected (default)
WKUP_GPIO0_2 MCU CAN1 Standby Output

‘0’ – Normal Mode

‘1’ – Standby Mode (default)
WKUP_GPIO0_56 MCU_RGMII1_Reset Output

‘0’ – Resets Ethernet physical Transceiver

‘1’ – Normal mode(default)
WKUP_GPIO0_7 Push-button Interrupt, User Defined/Wake S2R Input

'0' - Interrupt pending

'1' - Normal operation(default)
WKUP_GPIO0_6 Flash Memory Selection Output

'0' - OSPI0(default)

'1' - OCTAL NAND
WKUP_GPIO0_39 Interrupt from PMIC Input

‘0’ – Active Interrupt Request

‘1’ – No Interrupt Requested (default)
WKUP_GPIO0_30 Interrupt from OSPI Flash Input

‘0’ – Interrupt from OSPI

‘1’ – No interrupt(default)
WKUP_GPIO0_3 MCU Ethernet Interrupt Input

'0' - Interrupt pending

'1' - Normal operation(default)
WKUP_GPIO0_55 System Power Down Output

'0' - normal operation(default)

'1' - system power down
WKUP_GPIO0_69 MCU CAN0 Standby Output

‘0’ – Normal Mode

‘1’ – Standby Mode (default)
WKUP_GPIO0_57 Interrupt from I3C Gyroscope sensor Input

'0' - Interrupt pending

'1' - Normal operation(default)
WKUP_GPIO0_70 Push-button wake signal Input

'0' – wake signal

'1' - normal operation(default)
GPIO0_0 Push-button Interrupt, User Defined Input

'0' - Interrupt pending

'1' - Normal operation(default)
GPIO0_11 Push-button wake signal Input

'0' – wake signal

'1' - normal operation(default)
GPIO0_18

IO Expander Interrupt

(Bus I2C5)

 Input

'0' - interrupt pending

'1' - no interrupt(default)
GPIO0_25

IO Expander Interrupt

(Bus I2C0)

 Input

'0' - interrupt pending

'1' - no interrupt
GPIO0_8 SD Card IO Voltage Selection Output

0’ – SD Card IO Voltage is 1.8V

‘1’ – SD Card IO Voltage is 3.3V (default)
GPIO0_26 CSI2 Expansion Board Specific. I/O Camera Expansion Board Specific (Pin 18)
GPIO0_28 CSI2 Expansion Board Specific. I/O Camera Expansion Board Specific (Pin 22)
GPIO0_51

CP Board - PM I2C Mux selection.

GESI - Boosterpack_GPIO1

 Output

'0' - SOC_I2C2_SCL/SDA -> PM1_SCL/SDA

'1' - SOC_I2C2_SCL/SDA -> PM2_SCL/SDA
Note: GPIO functions sometimes share pins with other functions. The default state of these IO is set by the MCU_BOOTMODE and/or BOOTMODE pins. For the EVM, these pins are set via dip switches.
Table 3-4 GPIO Mapping for Expansion IO
I2C0/TCA6416 Addr: 0x21 Function Input/Output Remarks
P00 USB2.0 Mux Select line Output '0' – USBC path selected
'1' - USB Hub path is selected
P01 Select line for MAIN MUX Control #1 Output Refer schematic for the details of TRC/CAN UART/ Hyperlink sideband signals mux selection
P02 Select line for MAIN MUX Control #2 Output
P03 Select line for MAIN MUX Control #3 Output
P04 GESI Expansion Board Specific, RST# to RGMII PHY Output

‘0’ – RGMII Phy is Reset (default)

‘1’ –RGMII Phy is enabled/active
P05 Enable to DSI to eDP Bridge Output

0’ – DisplayPort Transmitter is disabled (default)

‘1’ – DisplayPort Transmitter is enabled
P06 Expansion Board Specific Bi-Dir ‘0’ – LIN Bus PHY is Disabled (default)
‘1’ – LIN Bus PHY is Enabled
P07 Standby signals for CAN Transceivers Output ‘0’ – Normal Mode
‘1’ – Standby Mode (default)
I2C5/TCA6408 Addr: 0x20 Function DIR/Level Remarks
P00 Camera Expansion Reset (#1 and #2) Output

0’ – Camera Expansion is disabled/Reset (default)

‘1’ – Camera Expansion is enabled/active
P01 Camera Expansion #1 GPIO #0 Bi-Dir Camera Expansion Board Specific (Pin 6)
P02 Camera Expansion #1 GPIO #1 Bi-Dir Camera Expansion Board Specific (Pin 8)
P03 Camera Expansion #1 GPIO #3 Bi-Dir Camera Expansion Board Specific (Pin 20)
P04 Camera Expansion #2 GPIO #1 Bi-Dir Camera Expansion Board Specific (Pin 8) (Reserved)
P05 Camera Expansion #2 GPIO #2 Bi-Dir Camera Expansion Board Specific (Pin 18) (Reserved)
P06 Camera Expansion #2 GPIO #3 Bi-Dir Camera Expansion Board Specific (Pin 20) (Reserved)
P07 Camera Expansion #2 GPIO #4 Bi-Dir Camera Expansion Board Specific (Pin 22) (Reserved)
I2C0/TCA6416 Addr: 0x20 Function DIR/Level Remarks
P00 PCIe1 mode selection Input

0’ – Processor/PCIe1 is Root Complex

‘1’ – Processor/PCIe1 is End Point

(Note Default is set via dip switch)
P01 PCIe1 PERSTz status Input

0’ – PCIe1 Reset is asserted

‘1’ – PCIe1 Reset is NOT asserted
P02

PCIe1 PERSTz Output

(Root Complex Mode)

 Output

‘0’ – PCIe1 Reset is asserted

‘1’ – PCIe1 Reset is NOT asserted
P03

PCIe1 PERSTz to PORz

(End Point Mode)

 Output

0’ – PCIe1 PERSTz is separate from PORz

‘1’ – PCIe1 PERSTz can control PORz
P04 PCIe0 mode selection Input

0’ – Processor/PCIe0 is Root Complex

‘1’ – Processor/PCIe0 is End Point

(Note Default is set via dip switch) (Reserved)
P05 PCIe0 PERSTz status Input

0’ – PCIe0 Reset is asserted

‘1’ – PCIe0 Reset is NOT asserted (Reserved)
P06

PCIe0 PERSTz Output

(Root Complex Mode)

 Output

‘0’ – PCIe0 Reset is asserted

‘1’ – PCIe0 Reset is NOT asserted (Reserved)
P07

PCIe0 PERSTz to PORz

(End Point Mode)

 Output

0’ – PCIe0 PERSTz is separate from PORz

‘1’ – PCIe0 PERSTz can control PORz(Reserved)
P10 PCIe1 Card Presence Detection Input

‘0’ – Card detected for PCIe1

‘1’ – Card NOT detected for PCIe1 (default)
P11 PCIe0 Card Presence Detection Input

0’ – Card detected for PCIe0

‘1’ – Card NOT detected for PCIe0 (default)(Reserved)
P12 External Clock enabled for PCIe0 Output

0’ – External Clock is NOT enabled for PCIe0

‘1’ – External Clock is enabled for PCIe0 (default)(Reserved)
P13 External Clock enabled for PCIe1 Output

0’ – External Clock is NOT enabled for PCIe1

‘1’ – External Clock is enabled for PCIe1 (default)
P14 GESI Expansion Mux Control Output Refer GESI expansion board user guide for more detail.
P15 GESI Expansion Mux Control Output
P16 GESI Expansion Mux Control Output
P17 GESI Expansion Ethernet Reset Output
I2C0/TCA6424 Addr: 0x22 Function DIR/Level Remarks
P00 Reset to apple authentication header Output

‘0’ – Device is in reset

‘1’ – Device normal operation (Reserved)
P01 MLB interface specific Output Reserved (MLB interface is not supported)
P02 SD Card Power Enable/Reset Output

‘0’ – SD Card Power is disabled/Reset

‘1’ – SD Card Power is enabled/active (default)
P03 USB Type C Power Enable Output

‘0’ – USB Type C Power is disabled

‘1’ – USB Type C Power is enabled (default)
P04 USB Type C Mode Selection #1 Input

‘00’ = DFP (Downstream Facing Port)

‘01’ = DRP (Dual Role Port)

1x’ = UFP (Upstream Facing Port)

(Note Default is set via dip switch [SW3 bits 3:4])
P05 USB Type C Mode Selection #2 Input
P06 ENABLE signal to MCAN3 Phy Output

MCAN3 PHY Enable

'0' - device disabled

'1' normal operation
P07 Standby signals for MCAN3 Transceivers Output

MCAN3 PHY Standby

'0' - device standby

'1' - normal operation)
P10 Power Measurement Bus Enable Output

0’ – Enabled access to INA from processor (I2C1) (default)

‘1’ – Disables access to INA from processor
P11 TRACE MUX Control Select line #1 on CP Output

Signal Mux Control, DIP switch allow default to either Trace or GPMC.

· TRACE with MIPI-60 Interface (set to '1 / 1')

· Expansion for GPMC Support (set to '1 / 0')

-P12 Audio Codec/Tuner Support (set to '0 / 1')
P12 TRACE MUX Control Select line #2 on CP Output
P13 MLB Mux selection Output Reserved (MLB interface is not supported)
P14 MCAN Interface mux selection Output

'0' - MCAN5

'1' - Expansion/EQEP
P15 MDIO Mux selection Output Expansion board specific (Not supported)
P16 PCIe Clk req Mux selection Output

'0' - PCIe Clk req Path is selected

'1' - UB926 GPIO path is selected
P17 External Clock Generator Reset Output

0’ – Expansion board is RESET

‘1’ – Expansion board is NOT reset (default)
P20 ENET Expansion power down Output Reserved(ENET expansion is not supported)
P21 ENET expansion reset Output Reserved(ENET expansion is not supported)
P22 ENET expansion I2C Mux sel Output Reserved(ENET expansion is not supported)
P23 ENET Expansion spare GPIO Bi-Dir Reserved(ENET expansion is not supported)
P24 Reset to M.2 PCIe Output Reserved(ENET expansion is not supported)
P25 User Dip Switch Input [SW3] Input

0’ – Dip Switch SW2 position 10 set to OFF

‘1’ – Dip Switch SW2 position 10 set to ON

(Note Default is set via dip switch SW3.10)
P26 User LED [LD9] Output

‘0’ – LED [LD9] is ON

‘1’ – LED [LD9] is OFF (default)
P27 User LED [LD8] Output

‘0’ – LED [LD8] is ON

‘1’ – LED [LD8] is OFF (default)
I2C3/TCA6408 Addr: 0x20 Function DIR/Level Remarks
P00 Audio Codec Enable/Reset Output

‘0’ – Audio Codec is disabled/Reset (default)

‘1’ – Audio Codec is enabled/active
P01 Reserved / Unused Bi-Dir Reserved / Unused
P02 RESET to UB926 Output Reserved (UB926 is not supported)
P03 UB926 PLL lock status Input Reserved (UB926 is not supported)
P04 Power enable to UB926 Output Reserved (UB926 is not supported)
P05 Tuner reset to UB926 Output Reserved (UB926 is not supported)
P06 Spare GPIO to UB926 Bi-Dir Reserved (UB926 is not supported)
P07 Unused NA NA
I2C4/TCA6408 Addr: 0x20 Function DIR/Level Remarks
P00 DisplayPort #0 Power Enable Output

‘0’ – DisplayPort Power is disabled (default)

‘1’ – DisplayPort Power is enabled
P01 DisplayPort #1 Power Enable Output

‘0’ – DisplayPort Power is disabled (default)

‘1’ – DisplayPort Power is enabled
P02 Power-Down to UB981 Output Reserved (UB981 is not supported)
P03 GPIO to UB981 #1 Bi-Dir Reserved (UB981 is not supported)
P04 GPIO to UB981 #2 Bi-Dir Reserved (UB981 is not supported)
P05 GPIO to UB981 #3 Bi-Dir Reserved (UB981 is not supported)
P06 GPIO to UB981 #4 Bi-Dir Reserved (UB981 is not supported)
P07 Power enable to UB981 Output Reserved (UB981 is not supported)