SPRUJ71 august   2023

 

  1.   1
  2.   C2000 F28P65x Series LaunchPad Development Kit
  3.   Trademarks
  4. 1Board Overview
    1. 1.1 Kit Contents
    2. 1.2 Features
    3. 1.3 Specifications
      1. 1.3.1 External Power Supply or Accessory Requirements
    4. 1.4 Using the F28P65x LaunchPad
    5. 1.5 BoosterPacks
    6. 1.6 Hardware Revisions
      1. 1.6.1 Revision A
  5. 2Software Development
    1. 2.1 Software Tools and Packages
    2. 2.2 F28P65x LaunchPad Demo Program
    3. 2.3 Programming and Running Other Software on the F28P65x LaunchPad
  6. 3Hardware Description
    1. 3.1 Functional Description and Connections
      1. 3.1.1  Microcontroller
      2. 3.1.2  Power Domains
      3. 3.1.3  LEDs
      4. 3.1.4  Encoder Connectors
      5. 3.1.5  FSI
      6. 3.1.6  CAN
      7. 3.1.7  EtherCAT
      8. 3.1.8  CLB
      9. 3.1.9  Boot Modes
      10. 3.1.10 BoosterPack Sites
      11. 3.1.11 Analog Voltage Reference
      12. 3.1.12 Differential ADC Header
      13. 3.1.13 Other Headers and Jumpers
        1. 3.1.13.1 XDS Isolation Block
        2. 3.1.13.2 BoosterPack Site 2 Power Isolation
        3. 3.1.13.3 Alternate Power
    2. 3.2 Debug Interface
      1. 3.2.1 XDS110 Debug Probe
      2. 3.2.2 XDS110 Output
      3. 3.2.3 Virtual COM Port
    3. 3.3 Alternate Routing
      1. 3.3.1 Overview
      2. 3.3.2 UART Routing
      3. 3.3.3 EQEP Routing
      4. 3.3.4 CAN Routing
      5. 3.3.5 FSI Routing
      6. 3.3.6 PWM DAC
  7. 4Board Design
    1. 4.1 Schematic
    2. 4.2 PCB Layout
    3. 4.3 BOM
    4. 4.4 LAUNCHXL-F28P65X Board Dimensions
  8. 5Frequently Asked Questions
  9. 6References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design

3.3.3 EQEP Routing

The LaunchPad has the ability to connect to two independent linear or rotary encoders through the F28P65x on-chip eQEP interfaces: Header J12 is connected to eQEP1 and header J13 is connected to eQEP2. By default, this connection is not active and the GPIOs are routed to the BoosterPack connectors. The 5 V eQEP input signals from the J12 and J13 connectors are stepped down through a TI SN74LVC8T245 Level Translator (U13) to 3.3 V. The signals are then routed through TI SN74LV4053A Triple 2-Channel Analog Multiplexer/Demultiplexer ICs (U11/U14). Switch S5 controls the select inputs of the ICs to configure the eQEP signal destinations to be either the J12/J13 connectors or BoosterPack headers, as described in Table 3-9.

Table 3-9 QEP Select Table - S5
QEP1 SEL (LEFT)QEP2 SEL (RIGHT)QEP1 Signals
(GPIO20/21/23)		QEP2 Signals
(GPIO24/79/103)
0 (down)0 (down)J12J13
0 (down)1 (up)J12BP Headers
1 (up)0 (down)BP HeadersJ13
1 (up)1 (up)BP HeadersBP Headers