SPRUJ73 December   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1. 1.1 Introduction
      1. 1.1.1 Read This First
        1. 1.1.1.1 Sitara MCU+ Academy
        2. 1.1.1.2 Important Usage Notes
    2. 1.2 Kit Contents
  6. 2Hardware Description
    1. 2.1 Component Identification
    2. 2.2 Power Requirements
      1. 2.2.1 Power Input Using USB Type-C Connector
      2. 2.2.2 Power Status LEDs
      3. 2.2.3 Power Tree
    3. 2.3 Functional Block Diagram
    4. 2.4 Header Information
    5. 2.5 Interfaces
      1. 2.5.1 ADC
      2. 2.5.2 LIN
      3. 2.5.3 MCAN
      4. 2.5.4 TRACE/GPMC Muxing Scheme
      5. 2.5.5 GPMC Memory Interface
        1. 2.5.5.1 PSRAM
        2. 2.5.5.2 GPMC Memory Footprint
        3. 2.5.5.3 NOR FLASH
      6. 2.5.6 TI 14-Pin Header
      7. 2.5.7 MIPI-60 Connector
    6. 2.6 HSEC Pinout
  7. 3Additional Information
    1. 3.1 If You Need Assistance
    2.     Trademarks
  8. 4References
    1. 4.1 Reference Documents
    2. 4.2 Other TI Components Used in This Design
  9. 5Revision History

2.5.5.2 GPMC Memory Footprint

The AM263x controlCARD Docking Station has a 56-pin QFN-SMD package pinout for the GPMC0 peripheral on the AM263x SoC.

GUID-20230201-SS0I-BWSS-4HWD-QXDXKXRRDV0Z-low.png Figure 2-13 GPMC Memory Footprint

Custom PCBs with memory types supported by the AM263x SoC can be soldered to this footprint, giving the user more flexibility in developing with different memory types, and not being restricted to the on-board PSRAM module. A reference design for a NOR FLASH PCB is included with the design package for the AM263x controlCARD Docking Station. Below is the pinout for the memory footprint.

Note: Rev A of the TMDSHSECDOCK-AM263 requires a blue-wire fix to supply the GPMC footprint with 3.3V. Pins 1 and 52 of the footprint are electrically connected together, but not to the 3.3V supply. Blue-wire from nearby header J23 to either of these pins to supply the footprint with 3.3V.

Table 2-16 GPMC Memory Footprint Pinout
Pin Signal Description
1 VDD_3V3_SYS 3.3V System Supply
2 GPMC0_A0 GPMC Address 0 Output. Only used to effectively address 8-bit data non-multiplexed memories
3 GPMC0_A1 GPMC Address 1 Output in A/D non-multiplexed mode and Address 17 in A/D multiplexed mode
4 GPMC0_A2 GPMC Address 2 Output in A/D non-multiplexed mode and Address 18 in A/D multiplexed mode
5 GPMC0_A3 GPMC Address 3 Output in A/D non-multiplexed mode and Address 19 in A/D multiplexed mode
6 GPMC0_A4 GPMC Address 4 Output in A/D non-multiplexed mode and Address 20 in A/D multiplexed mode
7 GPMC0_A5 GPMC Address 5 Output in A/D non-multiplexed mode and Address 21 in A/D multiplexed mode
8 GPMC0_A6 GPMC Address 6 Output in A/D non-multiplexed mode and Address 22 in A/D multiplexed mode
9 GPMC0_A7 GPMC Address 7 Output in A/D non-multiplexed mode and Address 23 in A/D multiplexed mode
10 GPMC0_A8 GPMC Address 8 Output in A/D non-multiplexed mode and Address 24 in A/D multiplexed mode
11 GPMC0_A9 GPMC Address 9 Output in A/D non-multiplexed mode and Address 25 in A/D multiplexed mode
12 GPMC0_A10 GPMC Address 10 Output in A/D non-multiplexed mode and Address 26 in A/D multiplexed mode
13 GPMC0_A11 GPMC Address 11 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode
14 GPMC0_A12 GPMC Address 12 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode
15 GPMC0_A13 GPMC Address 13 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode
16 GPMC0_A14 GPMC Address 14 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode
17 GPMC0_A15 GPMC Address 15 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode
18 GPMC0_A16 GPMC Address 16 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode
19 GPMC0_A17 GPMC Address 17 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode
20 GPMC0_A18 GPMC Address 18 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode
21 GPMC0_A19 GPMC Address 19 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode
22 GPMC0_A20 GPMC Address 20 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode
23 GPMC0_A21 GPMC Address 21 Output in A/D non-multiplexed mode and unused in A/D multiplexed mode
24 GND Ground
25 GPMC0_AD0 GPMC Data 0 Input/Output in A/D non-multiplexed mode and additionally Address 1 Output in A/D multiplexed mode
26 GPMC0_AD1 GPMC Data 1 Input/Output in A/D non-multiplexed mode and additionally Address 2 Output in A/D multiplexed mode
27 GPMC0_AD2 GPMC Data 2 Input/Output in A/D non-multiplexed mode and additionally Address 3 Output in A/D multiplexed mode
28 GPMC0_AD3 GPMC Data 3 Input/Output in A/D non-multiplexed mode and additionally Address 4 Output in A/D multiplexed mode
29 GPMC0_AD4 GPMC Data 4 Input/Output in A/D non-multiplexed mode and additionally Address 5 Output in A/D multiplexed mode
30 GPMC0_AD5 GPMC Data 5 Input/Output in A/D non-multiplexed mode and additionally Address 6 Output in A/D multiplexed mode
31 GPMC0_AD6 GPMC Data 6 Input/Output in A/D non-multiplexed mode and additionally Address 7 Output in A/D multiplexed mode
32 GPMC0_AD7 GPMC Data 7 Input/Output in A/D non-multiplexed mode and additionally Address 8 Output in A/D multiplexed mode
33 GPMC0_AD8 GPMC Data 8 Input/Output in A/D non-multiplexed mode and additionally Address 9 Output in A/D multiplexed mode
34 GPMC0_AD9 GPMC Data 9 Input/Output in A/D non-multiplexed mode and additionally Address 10 Output in A/D multiplexed mode
35 GPMC0_AD10 GPMC Data 10 Input/Output in A/D non-multiplexed mode and additionally Address 11 Output in A/D multiplexed mode
36 GPMC0_AD11 GPMC Data 11 Input/Output in A/D non-multiplexed mode and additionally Address 12 Output in A/D multiplexed mode
37 GPMC0_AD12 GPMC Data 12 Input/Output in A/D non-multiplexed mode and additionally Address 13 Output in A/D multiplexed mode
38 GPMC0_AD13 GPMC Data 13 Input/Output in A/D non-multiplexed mode and additionally Address 14 Output in A/D multiplexed mode
39 GPMC0_AD14 GPMC Data 14 Input/Output in A/D non-multiplexed mode and additionally Address 15 Output in A/D multiplexed mode
40 GPMC0_AD15 GPMC Data 15 Input/Output in A/D non-multiplexed mode and additionally Address 16 Output in A/D multiplexed mode
41 GPMC0_OEN_REN GPMC Output Enable (active low) or Read Enable (activelow)
42 GPMC0_WEN GPMC Write Enable (active low)
43 GPMC0_BE0N_CLE GPMC Lower-Byte Enable (active low) or Command Latch Enable
44 GPMC0_BE1 GPMC Upper-Byte Enable (active low)
45 GPMC0_CSN0 GPMC Chip Select 0 (active low)
46 GPMC0_WPN GPMC Flash Write Protect (active low)
47 GPMC0_WAIT0 GPMC External Indication of Wait
48 GPIO45 General Purpose Input/Output
49 GPIO48 General Purpose Input/Output
50 GPIO46 General Purpose Input/Output
51 GPMC0_CLK GPMC Clock
52 VDD_3V3_SYS 3.3V System Supply
53 NC -
54 GND Ground
55 GND Ground
56 GND Ground