SPRUJ93 august   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1.     Preface: Read This First
      1. 1.1.1 Sitara™ MCU+ Academy
      2. 1.1.2 If You Need Assistance
      3. 1.1.3 Important Usage Notes
    2. 1.1 Introduction
    3. 1.2 Kit Contents
    4. 1.3 Specification
    5. 1.4 Device Information
    6. 1.5 HSEC 180-pin Control Card Docking Station
    7. 1.6 Security
  6. 2Hardware
    1. 2.1  Functional Block Diagram
    2. 2.2  Component Identification
    3. 2.3  Power Requirements
      1. 2.3.1 Power Input Using USB Type-C Connector
      2. 2.3.2 Power Status LEDs
      3. 2.3.3 Power Tree
      4. 2.3.4 Power Sequence
      5. 2.3.5 PMIC
    4. 2.4  Reset
    5. 2.5  Clock
    6. 2.6  Boot Mode Selection
    7. 2.7  JTAG Path Selection
    8. 2.8  Header Information
    9. 2.9  GPIO Mapping
    10. 2.10 Push Buttons
    11. 2.11 Test Points
    12. 2.12 Interfaces
      1. 2.12.1  Memory Interface
        1. 2.12.1.1 QSPI
        2. 2.12.1.2 Board ID EEPROM
      2. 2.12.2  Ethernet Interface
        1. 2.12.2.1 RGMII
        2. 2.12.2.2 PRU-ICSS
        3. 2.12.2.3 LED Indication in RJ45 Connector
      3. 2.12.3  I2C
      4. 2.12.4  Industrial Application LEDs
      5. 2.12.5  SPI
      6. 2.12.6  UART
      7. 2.12.7  MCAN
      8. 2.12.8  FSI
      9. 2.12.9  JTAG
      10. 2.12.10 Test Automation Header
      11. 2.12.11 LIN
      12. 2.12.12 MMC
      13. 2.12.13 ADC and DAC
    13. 2.13 HSEC Pinout and Pinmux Mapping
  7. 3Software
    1. 3.1 SDK Installation
  8. 4Hardware Design Files
  9. 5Additional Information
    1. 5.1 Trademarks
    2. 5.2 E1 Design Hardware Modifications
  10. 6References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design

2.8 Header Information

This version of the AM263x Control Card has 11 different headers. For the locations of each header, refer to Section 2.2. The signal details for each header pin is detailed below.

  • Test Automation Bootmode Control Header
    • For more information about the Test Automation Header, refer to Section 2.12.10
Table 2-6 Test Automation Header
Designator Pin 1 Pin 2
J3 TA_GPIO3 DGND
  • MCAN Header
    • For more information about the MCAN interface, refer to Section 2.12.7
Table 2-7 MCAN Header
Designator Pin 1 Pin 2 Pin 3
J5 MCAN1_CAN_H DGND MCAN1_CAN_L
  • FSI Header
    • For more information about the FSI Interface, refer to Section 2.12.8
Table 2-8 FSI Header
Designator Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10
J6 FSIRX2_CLK FSITX2_CLK DGND DGND FSIRX2_DATA0 FSITX2_DATA0 FSIRX2_DATA1 FSITX2_DATA1 DGND VSYS_3V3A
  • PRU-ICSS IEP Headers
Table 2-9 PRU-ICSS IEP Headers
Designator Pin 1 Pin 2
J8 PR0_IEP0_EDIO_DATA_IN_OUT_31 DGND
J9 PR0_IEP0_EDC_SYNC_OUT1 DGND
J10 PR0_IEP0_EDIO_DATA_IN_OUT_30 DGND
J11 PR0_IEP0_EDC_SYNC_OUT0 DGND
  • LIN Headers
Table 2-10 LIN Headers
Designator Pin 1 Pin 2 Pin 3
J32 VLIN LIN DGND
J33 VBAT_LIN DGND N/A
  • PMIC Headers
Table 2-11 PMIC Headers
Designator Pin 1 Pin 2
J35 IGNITION DGND
J36 CANWU DGND