SPRUJ93 august   2023

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1.     Preface: Read This First
      1. 1.1.1 Sitara™ MCU+ Academy
      2. 1.1.2 If You Need Assistance
      3. 1.1.3 Important Usage Notes
    2. 1.1 Introduction
    3. 1.2 Kit Contents
    4. 1.3 Specification
    5. 1.4 Device Information
    6. 1.5 HSEC 180-pin Control Card Docking Station
    7. 1.6 Security
  6. 2Hardware
    1. 2.1  Functional Block Diagram
    2. 2.2  Component Identification
    3. 2.3  Power Requirements
      1. 2.3.1 Power Input Using USB Type-C Connector
      2. 2.3.2 Power Status LEDs
      3. 2.3.3 Power Tree
      4. 2.3.4 Power Sequence
      5. 2.3.5 PMIC
    4. 2.4  Reset
    5. 2.5  Clock
    6. 2.6  Boot Mode Selection
    7. 2.7  JTAG Path Selection
    8. 2.8  Header Information
    9. 2.9  GPIO Mapping
    10. 2.10 Push Buttons
    11. 2.11 Test Points
    12. 2.12 Interfaces
      1. 2.12.1  Memory Interface
        1. 2.12.1.1 QSPI
        2. 2.12.1.2 Board ID EEPROM
      2. 2.12.2  Ethernet Interface
        1. 2.12.2.1 RGMII
        2. 2.12.2.2 PRU-ICSS
        3. 2.12.2.3 LED Indication in RJ45 Connector
      3. 2.12.3  I2C
      4. 2.12.4  Industrial Application LEDs
      5. 2.12.5  SPI
      6. 2.12.6  UART
      7. 2.12.7  MCAN
      8. 2.12.8  FSI
      9. 2.12.9  JTAG
      10. 2.12.10 Test Automation Header
      11. 2.12.11 LIN
      12. 2.12.12 MMC
      13. 2.12.13 ADC and DAC
    13. 2.13 HSEC Pinout and Pinmux Mapping
  7. 3Software
    1. 3.1 SDK Installation
  8. 4Hardware Design Files
  9. 5Additional Information
    1. 5.1 Trademarks
    2. 5.2 E1 Design Hardware Modifications
  10. 6References
    1. 6.1 Reference Documents
    2. 6.2 Other TI Components Used in This Design

2.6 Boot Mode Selection

The bootmode for the AM263x is selected by either the DIP switch (SW3) or the test automation header. The test automation header uses an I2C IO expansion buffer to drive the bootmode when PORz is toggled. The supported boot modes are as shown in Supported Boot Modes.

Table 2-4 Supported Boot Modes
Boot Mode/Peripheral Boot Media/Host Notes
QSPI (4S) - Quad Read Mode QSPI Flash Download and boot SBL from QSPI flash in quad read mode. Attempt Primary SBL, followed by Secondary SBL if primary loading fails.
UART External Host Download and boot SBL from UART. Device is expected to get SBL from UART. Device supports the XMODEM protocol for download over UART.
QSPI (1S) - Single Read Mode QSPI Flash Download and boot SBL from QSPI flash in single read mode. Attempt Primary SBL, followed by Secondary SBL if primary loading fails.
QSPI (4S) - Quad Read UART Fallback Mode QSPI Flash / External Host Download and boot SBL from QSPI flash in quad read mode. Attempt Primary SBL, followed by Secondary SBL if primary loading fails. If Secondary SBL also fails then boot from external host via UART interface.
QSPI (1S) - Single Read UART Fallback Mode QSPI Flash / External Host Download and boot SBL from QSPI flash in single read mode. Attempt Primary SBL, followed by Secondary SBL if primary loading fails. If Secondary SBL also fails then boot from external host via UART interface.
DevBoot N/A No SBL. Used for development purposes only.
GUID-20211120-SS0I-GMVX-PPMM-1WX6HGKX31VC-low.png Figure 2-14 SW3 Switch Positions
Table 2-5 Boot-Mode Selection Table
Boot Mode SPI0_D0_pad (SOP3) SPI0_CLK_pad (SOP2) QSPI_D1 (SOP1) QSPI_D0 (SOP0)
QSPI (4S) - Quad Read Mode 0 0 0 0
UART 0 0 0 1
QSPI (1S) - Single Read Mode 0 0 1 0
QSPI (4S) - Quad Read UART Fallback Mode 0 1 0 0
QSPI (1S) - Single Read UART Fallback Mode 0 1 0 1
DevBoot 1 0 1 1
Unsupported Boot Mode All other combinations not defined above