SPRUJ97 June   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 Key Features and Interfaces
    2. 2.2 EVM Compatibility
    3. 2.3 Assembly Instructions
    4. 2.4 Power Budget Considerations
    5. 2.5 Interfaces
      1. 2.5.1 EVM Interface
      2. 2.5.2 Sensor Interface / Coax
      3. 2.5.3 Sensor Interface / Twisted Pair
    6. 2.6 Circuit Details
      1. 2.6.1 Interface Mapping
      2. 2.6.2 I2C Address Map
      3. 2.6.3 GPIO Map
      4. 2.6.4 Identification EEPROM
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  10. 4Compliance Information
    1. 4.1 Thermal Compliance
    2. 4.2 EMC, EMI, and ESD Compliance
  11. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
    2. 5.2 Trademarks
  12. 6Related Documentation

2.5.1 EVM Interface

The add-on module supports two 40-pin high speed connectors [J1] [J2] for interfacing with the base EVM or EVMs. The interface (two connectors) support three MIPI CSI2 receiver ports, each supporting up to 4-lanes of data. The interface also includes a control and configuration mechanism (I2C) and multiple IO for various interrupts and syncs are provided. This IO voltage level can be either 1.8V or 3.3V, and must match the IO power pin.

Power for the add-on module plus power for plug-in sensor modules is also supplied through the interface.

Table 2-2 Expansion Interface Pin Definition [J1]
Pin # Pin Name Description Direction

1

Power

Power (12-20V)

Input

2

I2C_SCL

I2C Clock

Bi-Dir

3

Power

 Power (12-20V)

Input

4

I2C_SDA

I2C Data

 Bi-Dir

5

CSI_0_CLK_P

CSI Port 0 Clock

Output

6

INTn_Port0

GPIO, see Table 3-6

Output

7

CSI_0_CLK_N

 CSI Port 0 Clock Output

8

 INTn_Port1 GPIO, see Table 3-6 Output

9

CSI_0_D0_P

CSI Port 0 Data Lane 0

 Output

10

REF_CLK

Optional reference clock for FPD-Link deserializer

Input

11

 CSI_0_D0_N CSI Port 0 Data Lane 0 Output

12

GND

Ground

13

 CSI_0_D1_P

CSI Port 0 Data Lane 1

 Output

14

 Reset GPIO, see Table 3-6

Input

15

 CSI_0_D1_N CSI Port 0 Data Lane 1 Output

16

GND

Ground

17

 CSI_0_D2_P

CSI Port 0 Data Lane 2

 Output

18

 Sync_Port0 GPIO, see Table 3-6 Bi-Dir

19

 CSI_0_D2_N CSI Port 0 Data Lane 2 Output
20 Open / Unused
21 CSI_0_D3_P CSI Port 0 Data Lane 3 Output
22 Sync_Port1 GPIO, see Table 3-6 Bi-Dir
23 CSI_0_D3_N CSI Port 0 Data Lane 3 Output
24 GND Ground
25 CSI_1_CLK_P CSI Port 1 Clock Output
26 CSI_1_D3_P CSI Port 1 Data Lane 3 Output
27 CSI_1_CLK_N CSI Port 1 Clock Output
28 CSI_1_D3_N CSI Port 1 Data Lane 3 Output
29 CSI_1_D0_P

CSI Port 1 Data Lane 0

 Output
30 Power_3V3 Power, 3.3V Input
31 CSI_1_D0_N CSI Port 1 Data Lane 0 Output
32

Power_3V3

 Power, 3.3V

Input

33

 CSI_1_D1_P

CSI Port 1 Data Lane 1

 Output

34

 Power_3V3 Power, 3.3V Input

35

 CSI_1_D1_N CSI Port 1 Data Lane 1 Output

36

 Power_3V3 Power, 3.3V Input

37

 CSI_1_D2_P

CSI Port 1 data lane 2

 Output

38

Power_IO

Power, IO voltage level (1.8V or 3.3V)

Input

39

 CSI_1_D2_N CSI Port 1 data lane 2 Output

40

 Power_IO Power, IO voltage level (1.8V or 3.3V)

Input

Table 2-3 Expansion Interface Pin Definition [J2]
Pin # Pin Name Description Direction
1 Power Power (12-20V) Input
2 Open / Unused
3 Power Power (12-20V) Input
4 Open / Unused
5 CSI_2_CLK_P

CSI Port 2 Clock

 Output
6 Open / Unused
7 CSI_2_CLK_N CSI Port 2 Clock Output
8 INTn_Port2 GPIO, see Table 3-6 Output
9 CSI_2_D0_P CSI Port 2 Data Lane 0 Output
10 Open / Unused
11 CSI_2_D0_N CSI Port 2 Data Lane 0 Output
12 GND Ground
13 CSI_2_D1_P CSI Port 2 Data Lane 1 Output
14 Open / Unused
15 CSI_2_D1_N CSI Port 2 Data Lane 1 Output
16 GND Ground
17 CSI_2_D2_P CSI Port 2 Data Lane 2 Output
18 Sync_Port2 GPIO, see Table 3-6 Bi-Dir
19 CSI_2_D2_N CSI Port 2 Data Lane 2 Output
20 Open/Unused
21 CSI_2_D3_P CSI Port 2 Data Lane 3 Output
22 Open / Unused
23 CSI_2_D3_N CSI Port 2 Data Lane 3 Output
24 GND Ground
25 Open / Unused
26 Open / Unused
27 Open / Unused
28 Open / Unused
29 Open / Unused
30 Power_3V3 Power, 3.3V Input
31 Open / Unused
32 Power_3V3 Power, 3.3V Input
33 Open / Unused
34 Power_3V3 Power, 3.3V Input
35 Open / Unused
36 Power_3V3 Power, 3.3V Input
37 Open / Unused
38 Power_IO Power, IO voltage level (1.8V or 3.3V) Input
39 Open / Unused
40 Power_IO Power, IO voltage level (1.8V or 3.3V) Input