SPRUJA2 November   2023

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 Specification
  7. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Key Features
      1. 2.2.1 Processor
      2. 2.2.2 Power Supply
      3. 2.2.3 Memory
      4. 2.2.4 JTAG/Emulator
      5. 2.2.5 Supported Interfaces and Peripherals
      6. 2.2.6 Expansion Connectors/Headers
    3. 2.3  Interface Mapping
    4. 2.4  Power ON/OFF Procedure
      1. 2.4.1 Power ON Procedure
      2. 2.4.2 Power OFF Procedure
      3. 2.4.3 Test Points
    5. 2.5  Clocking
      1. 2.5.1 Peripheral Ref Clock
    6. 2.6  Reset
    7. 2.7  CSI Interface
    8. 2.8  OLDI Interface
    9. 2.9  DSI Interface
    10. 2.10 Audio Codec Interface
    11. 2.11 HDMI Display Interface
    12. 2.12 JTAG Interface
    13. 2.13 Test Automation Header
    14. 2.14 UART Interface
    15. 2.15 USB Interface
      1. 2.15.1 USB 2.0 Type A Interface
      2. 2.15.2 USB 2.0 Type C Interface
    16. 2.16 Memory Interfaces
      1. 2.16.1 LPDDR4 Interface
      2. 2.16.2 OSPI Interface
      3. 2.16.3 MMC Interfaces
        1. 2.16.3.1 MMC0 - eMMC Interface
        2. 2.16.3.2 MMC1 - Micro SD Interface
        3. 2.16.3.3 MMC2 - M.2 Key E Interface
      4. 2.16.4 Board ID EEPROM
    17. 2.17 Ethernet Interface
      1. 2.17.1 CPSW Ethernet PHY Strapping
      2. 2.17.2 CPSW Ethernet PHY1 Default Configuration
      3. 2.17.3 CPSW Ethernet PHY2 Default Configuration
    18. 2.18 GPIO Port Expander
    19. 2.19 GPIO Mapping
    20. 2.20 Power
      1. 2.20.1 Power Requirement
      2. 2.20.2 Power Input
      3. 2.20.3 Power Supply
      4. 2.20.4 Power Sequencing
      5. 2.20.5 AM62P SoC Power
      6. 2.20.6 Current Monitoring
    21. 2.21 EVM User Setup/Configuration
      1. 2.21.1 DIP Switches
      2. 2.21.2 Boot Modes
      3. 2.21.3 User Test LEDs
    22. 2.22 Expansion Headers
      1. 2.22.1 User Expansion Connector
      2. 2.22.2 MCU Connector
      3. 2.22.3 GPMC NAND (x8) Connector
    23. 2.23 Interrupt
    24. 2.24 I2C Address Mapping
  8. 3Hardware Design Files
  9. 4Compliance Information
    1. 4.1 Compliance and Certifications
  10. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
      1. 5.1.1 Issue 1 - Watchdog Reset
      2. 5.1.2 Issue 2 - Power Down Sequence
    2. 5.2 Trademarks

2.13 Test Automation Header

AM62P SK EVM has an optional 40-pin test automation header (FH12A-40S-0.5SH) to allow any external controller to manipulate some basic operations like Power Down, POR, Warm Reset, and Boot Mode control.

The Test Automation Circuit is powered by the 3.3V supply generated by an Always On regulator Mfr. Part# LM5141QRGETQ1. The SOC’s I2C1 instance is connected to the test automation header. Another I2C instance (BOOTMODE_I2C) from the Test Automation Header is connected to the 24-bit I2C boot mode IO Expander of Mfr. Part# TCA6424ARGJR to allow control of the boot modes for the AM62P SOC.

GUID-20231102-SS0I-XTMH-3RFK-WJ6QNFJZRKGV-low.png Figure 2-13 Test Automation Interface

The test automation has voltage translation circuits so that the controller is isolated from the I/O voltages used by the AM62P. Boot mode for the AM62P can be user controlled by either using DIP Switches or the test automation header through the I2C I/O Expander. Boot Mode Buffers are used to isolate the Boot Mode controls driven through DIP Switches or I2C I/O Expander. The boot mode can also be set using two 8-bit DIP switches on the board, which connects a pull-up resistor to the output of a buffer when the switch is set to the ON position and to a weaker pull-down resistor when set to OFF position. The outputs of the buffer are connected to the boot mode pins on the AM62P SOC and the output is only enabled when the boot mode is needed during a reset cycle.

When boot mode is to be set through Test Automation header, the required switch values are set at the I2C I/O expander output, which overwrites the DIP switch values to give the desired boot values to the SOC. The pins used for boot mode also have other functions which are automatically isolated by disabling the boot mode buffer during normal operation.

The power down signal from the Test automation header instructs the SK EVM to power down all the rails except for dedicated power supplies on the board. Similarly, PORZn signal provides a hard reset to the SOC and WARM_RESETn for a warm reset to the SOC.

Table 2-8 Test Automation Connector (J29) Pinout
Pin no. Signal IO Direction Pin no. Signal IO Direction
1 VCC3V3_TA Power 21 NC NA
2 VCC3V3_TA Power 22 NC NA
3 VCC3V3_TA Power 23 NC NA
4 NC NA 24 NC NA
5 NC NA 25 DGND Power
6 NC NA 26 TEST_POWERDOWN Input
7 DGND Power 27 TEST_PORZn Input
8 NC NA 28 TEST_WARMRESETn Input
9 NC NA 29 NC NA
10 NC NA 30 TEST_GPIO1 Input
11 NC NA 31 TEST_GPIO2 Bidirectional
12 NC NA 32 TEST_GPIO3 Input
13 NC NA 33 TEST_GPIO4 Input
14 NC NA 34 DGND Power
15 NC NA 35 NC NA
16 DGND Power 36 SoC_I2C1_TA_SCL Bidirectional
17 NC NA 37 BOOTMODE_I2C_SCL Bidirectional
18 NC NA 38 SoC_I2C1_TA_SDA Bidirectional
19 NC NA 39 BOOTMODE_I2C_SDA Bidirectional
20 NC NA 40 DGND Power