SPRUJA9 January   2024

 

  1.   1
  2.   Description
  3.   Features
  4.   4
  5. 1Evaluation Module Overview
    1.     Preface: Read This First
      1. 1.1.1 Sitara MCU+ Academy
      2. 1.1.2 If You Need Assistance
    2. 1.1 Introduction
    3. 1.2 Kit Contents
    4. 1.3 Device Information
  6. 2Hardware
    1. 2.1 Component Identification
    2. 2.2 Power Requirements
      1. 2.2.1 Power Tree
    3. 2.3 Functional Block Diagram
    4. 2.4 Header Information
    5. 2.5 Test Points
    6. 2.6 Interfaces
      1. 2.6.1 Automotive Ethernet PHY
      2. 2.6.2 Automotive Ethernet PHY Strapping Resistors
    7. 2.7 Integration Guide
      1. 2.7.1 Board Dimensions
      2. 2.7.2 DF40GB Connector
      3. 2.7.3 Mounting Holes
      4. 2.7.4 MATEnet Ethernet Connector
  7. 3Hardware Design Files
  8. 4Additional Information
    1. 4.1 Trademarks
  9. 5References
    1. 5.1 Reference Documents
    2. 5.2 Compatible Sitara™ MCU AM2x EVMs
    3. 5.3 Other TI Components Used in This Design

2.6.2 Automotive Ethernet PHY Strapping Resistors

The Ethernet PHY uses many functional pins as strap option to place the device into specific modes of operation.

GUID-D936758A-F5C1-4A7B-9DBE-216992BFF79C-low.png Figure 2-6 Automotive Ethernet PHY Strapping Resistors
Table 2-3 Recommended 3-level Strap Resistor Ratios
MODE IDEAL RH (kΩ) for VDDIO = 3.3V
1 OPEN
2 13
3 4.5
Table 2-4 Recommended 2-level Strap Resistor
MODE IDEAL RH (kΩ)
1 OPEN
2 2.49
Table 2-5 Industrial 1 Gbit Ethernet PHY Strapping Resistors
Functional Pin Default Mode Mode on DP83TG720-EVM-AM2 Pull-Up Function
RX_D0 1 1 OPEN MAC Interface: RGMII (Align mode)
RX_D1 1 1 OPEN
RX_D2 1 2 (2-level) 2.49kΩ
RX_CTRL 2 (3-level) 13kΩ PHY address: 0xC (0b01100)
STRP_1 2 (3-level) 13kΩ
LED_0 1 2 (2-level) 2.49kΩ MS=0
LED_1 1 1 OPEN Autonomous