SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The 18-bit RGB source data (typically dithered to 18-bit) coming from the DSS DISPC video port is expected to have the component mapping shown in Table 12-442. The DSS0_VP_DSS_OLDI_CFG[8] MSB register bit must be set for 18-bit input. Only 18-bit LVDS output mapping is supported with this input type.
23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Unused | R[5:0] | G[5:0] | B[5:0] |