SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The R5F provides native ECC and parity support on all related memories, generating and checking the redundancy automatically. The R5F can also monitor any ECC errors on it's SoC buses and bridges through the ECC aggregator. The methods for checking and reporting errors are available in the Arm Cortex-R5 Technical Reference Manual.
The R5FSS adds the capability of testing this logic by allowing errors (single and double bit) to be injected into memories (for testing purposes) via an ECC aggregator (per core). Note that because the R5FSS ECC aggregator is only used in error-injection mode, it only supports a subset of the generic ECC aggregator functionality in the device.
For a detailed description of the generic ECC aggregator functionality, see ECC Aggregator. For register descriptions of the WKUP_R5FSS aggregators, see R5FSS_CPU0_ECC_AGGR_CFG_REGS Registers and R5FSS_CPU1_ECC_AGGR_CFG_REGS Registers, respectively.
Table 7-34 provides the RAM ID. This is needed for bit field [10-0] ECC_VECTOR in the corresponding R5FSS_CPU0_VECTORR5FSS_CPU0_VECTOR register (part of the ECC aggregator register space).
RAM ID | Memory Name |
---|---|
0 | CPU0 ITAG RAM0 |
1 | CPU0 ITAG RAM1 |
2 | CPU0 ITAG RAM2 |
3 | CPU0 ITAG RAM3 |
4 | CPU0 IDATA BANK0 |
5 | CPU0 IDATA BANK1 |
6 | CPU0 IDATA BANK2 |
7 | CPU0 IDATA BANK3 |
8 | CPU0 DTAG RAM0 |
9 | CPU0 DTAG RAM1 |
10 | CPU0 DTAG RAM2 |
11 | CPU0 DTAG RAM3 |
12 | CPU0 DDIRTY RAM |
13 | CPU0 DDATA RAM0 |
14 | CPU0 DDATA RAM1 |
15 | CPU0 DDATA RAM2 |
16 | CPU0 DDATA RAM3 |
17 | CPU0 DDATA RAM4 |
18 | CPU0 DDATA RAM5 |
19 | CPU0 DDATA RAM6 |
20 | CPU0 DDATA RAM7 |
21 | CPU0 ATCM BANK0 |
22 | CPU0 ATCM BANK1 |
23 | CPU0 B0TCM BANK0 |
24 | CPU0 B0TCM BANK1 |
25 | CPU0 B1TCM BANK0 |
26 | CPU0 B1TCM BANK1 |
27 | CPU0 VIM RAM |