SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Interrupt Input Line | Interrupt ID | Source Interrupt |
---|---|---|
HSM0_NVIC_IN_8 | 8 | SMS0_DMTIMER_0_INTR_PEND_0 |
HSM0_NVIC_IN_10 | 10 | SMS0_DMTIMER_1_INTR_PEND_0 |
HSM0_NVIC_IN_11 | 11 | SMS0_RAT_0_EXP_INTR_0 |
HSM0_NVIC_IN_14 | 14 | GLUELOGIC_INVERTED_WKUP_RDY_OUT_0 |
HSM0_NVIC_IN_16 | 16 | SMS0_RTI_0_WDG_INTR_4 |
HSM0_NVIC_IN_17 | 17 | SMS0_RTI_0_WDG_INTR_0 |
HSM0_NVIC_IN_18 | 18 | SMS0_RTI_0_WDG_INTR_1 |
HSM0_NVIC_IN_19 | 19 | SMS0_RTI_0_WDG_INTR_2 |
HSM0_NVIC_IN_20 | 20 | SMS0_RTI_0_WDG_INTR_3 |
HSM0_NVIC_IN_32 | 32 | SMS0_DMTIMER_2_INTR_PEND_0 |
HSM0_NVIC_IN_34 | 34 | SMS0_DMTIMER_3_INTR_PEND_0 |
HSM0_NVIC_IN_36 | 36 | SMS0_DBG_AUTH_0_DBG_AUTH_0 |
HSM0_NVIC_IN_38 | 38 | SMS0_AESEIP38T_0_AES_SINTREQUEST_S_0 |
HSM0_NVIC_IN_39 | 39 | SMS0_AESEIP38T_0_AES_SINTREQUEST_P_0 |
HSM0_NVIC_IN_50 | 50 | MAILBOX0_MAILBOX_CLUSTER_0_MAILBOX_CLUSTER_PEND_1 |
HSM0_NVIC_IN_51 | 51 | CPSW0_CPTS_COMP_0 |
HSM0_NVIC_IN_52 | 52 | PCIE0_PCIE_CPTS_COMP_0 |
HSM0_NVIC_IN_55 | 55 | MAILBOX0_MAILBOX_CLUSTER_1_MAILBOX_CLUSTER_PEND_1 |
HSM0_NVIC_IN_56 | 56 | MAILBOX0_MAILBOX_CLUSTER_2_MAILBOX_CLUSTER_PEND_1 |
HSM0_NVIC_IN_57 | 57 | MAILBOX0_MAILBOX_CLUSTER_3_MAILBOX_CLUSTER_PEND_1 |
HSM0_NVIC_IN_58 | 58 | WKUP_PBIST1_DFT_PBIST_CPU_0 |
HSM0_NVIC_IN_68 | 68 | EPWM0_EPWM_ETINT_0 |
HSM0_NVIC_IN_69 | 69 | EPWM1_EPWM_ETINT_0 |
HSM0_NVIC_IN_70 | 70 | EPWM2_EPWM_ETINT_0 |
HSM0_NVIC_IN_71 | 71 | EQEP0_EQEP_INT_0 |
HSM0_NVIC_IN_72 | 72 | EQEP1_EQEP_INT_0 |
HSM0_NVIC_IN_73 | 73 | EQEP2_EQEP_INT_0 |
HSM0_NVIC_IN_74 | 74 | ECAP0_ECAP_INT_0 |
HSM0_NVIC_IN_75 | 75 | ECAP1_ECAP_INT_0 |
HSM0_NVIC_IN_76 | 76 | ECAP2_ECAP_INT_0 |
HSM0_NVIC_IN_78 | 78 | WKUP_MCU_GPIOMUX_INTROUTER0_OUTP_4 |
HSM0_NVIC_IN_79 | 79 | WKUP_MCU_GPIOMUX_INTROUTER0_OUTP_5 |
HSM0_NVIC_IN_80 | 80 | WKUP_MCU_GPIOMUX_INTROUTER0_OUTP_6 |
HSM0_NVIC_IN_81 | 81 | WKUP_MCU_GPIOMUX_INTROUTER0_OUTP_7 |
HSM0_NVIC_IN_83 | 83 | MCRC64_0_INT_MCRC_0 |
HSM0_NVIC_IN_84 | 84 | MCSPI0_INTR_SPI_0 |
HSM0_NVIC_IN_85 | 85 | MCU_MCSPI0_INTR_SPI_0 |
HSM0_NVIC_IN_86 | 86 | MCU_MCSPI1_INTR_SPI_0 |
HSM0_NVIC_IN_87 | 87 | MCSPI1_INTR_SPI_0 |
HSM0_NVIC_IN_88 | 88 | MCSPI2_INTR_SPI_0 |
HSM0_NVIC_IN_89 | 89 | UART0_USART_IRQ_0 |
HSM0_NVIC_IN_90 | 90 | UART1_USART_IRQ_0 |
HSM0_NVIC_IN_91 | 91 | UART2_USART_IRQ_0 |
HSM0_NVIC_IN_92 | 92 | UART3_USART_IRQ_0 |
HSM0_NVIC_IN_93 | 93 | UART4_USART_IRQ_0 |
HSM0_NVIC_IN_94 | 94 | UART5_USART_IRQ_0 |
HSM0_NVIC_IN_95 | 95 | UART6_USART_IRQ_0 |
HSM0_NVIC_IN_96 | 96 | MCU_UART0_USART_IRQ_0 |
HSM0_NVIC_IN_97 | 97 | I2C0_POINTRPEND_0 |
HSM0_NVIC_IN_98 | 98 | I2C1_POINTRPEND_0 |
HSM0_NVIC_IN_99 | 99 | I2C2_POINTRPEND_0 |
HSM0_NVIC_IN_100 | 100 | I2C3_POINTRPEND_0 |
HSM0_NVIC_IN_101 | 101 | MCU_I2C0_POINTRPEND_0 |
HSM0_NVIC_IN_102 | 102 | MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 |
HSM0_NVIC_IN_103 | 103 | MCAN0_MCANSS_MCAN_LVL_INT_0 |
HSM0_NVIC_IN_104 | 104 | MCAN0_MCANSS_MCAN_LVL_INT_1 |
HSM0_NVIC_IN_105 | 105 | MCU_MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 |
HSM0_NVIC_IN_106 | 106 | MCU_MCAN1_MCANSS_MCAN_LVL_INT_0 |
HSM0_NVIC_IN_107 | 107 | MCU_MCAN1_MCANSS_MCAN_LVL_INT_1 |
HSM0_NVIC_IN_108 | 108 | MCU_MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 |
HSM0_NVIC_IN_109 | 109 | MCU_MCAN0_MCANSS_MCAN_LVL_INT_0 |
HSM0_NVIC_IN_110 | 110 | MCU_MCAN0_MCANSS_MCAN_LVL_INT_1 |
HSM0_NVIC_IN_111 | 111 | GLUELOGIC_MAIN_DCC_DONE_GLUE_DCC_DONE_0 |
HSM0_NVIC_IN_112 | 112 | MCU_DCC0_INTR_DONE_LEVEL_0 |
HSM0_NVIC_IN_113 | 113 | MCASP0_XMIT_INTR_PEND_0 |
HSM0_NVIC_IN_114 | 114 | MCASP1_XMIT_INTR_PEND_0 |
HSM0_NVIC_IN_115 | 115 | MCASP2_XMIT_INTR_PEND_0 |
HSM0_NVIC_IN_116 | 116 | MCASP0_REC_INTR_PEND_0 |
HSM0_NVIC_IN_117 | 117 | MCASP1_REC_INTR_PEND_0 |
HSM0_NVIC_IN_118 | 118 | MCASP2_REC_INTR_PEND_0 |
HSM0_NVIC_IN_119 | 119 | C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_16 |
HSM0_NVIC_IN_120 | 120 | C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_17 |
HSM0_NVIC_IN_121 | 121 | C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_18 |
HSM0_NVIC_IN_122 | 122 | C7X256V0_CLEC_SOC_EVENTS_OUT_LEVEL_19 |
HSM0_NVIC_IN_123 | 123 | MCU_DCC1_INTR_DONE_LEVEL_0 |
HSM0_NVIC_IN_124 | 124 | MCAN1_MCANSS_MCAN_LVL_INT_0 |
HSM0_NVIC_IN_125 | 125 | MCAN1_MCANSS_MCAN_LVL_INT_1 |
HSM0_NVIC_IN_126 | 126 | MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 |
HSM0_NVIC_IN_127 | 127 | C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_16 |
HSM0_NVIC_IN_128 | 128 | C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_17 |
HSM0_NVIC_IN_129 | 129 | C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_18 |
HSM0_NVIC_IN_130 | 130 | C7X256V1_CLEC_SOC_EVENTS_OUT_LEVEL_19 |
HSM0_NVIC_IN_152 | 152 | SMS0_RAT_1_EXP_INTR_0 |
HSM0_NVIC_IN_155 | 155 | SMS0_RTI_1_WDG_INTR_4 |
HSM0_NVIC_IN_156 | 156 | SMS0_RTI_1_WDG_INTR_0 |
HSM0_NVIC_IN_157 | 157 | SMS0_RTI_1_WDG_INTR_1 |
HSM0_NVIC_IN_158 | 158 | SMS0_RTI_1_WDG_INTR_2 |
HSM0_NVIC_IN_159 | 159 | SMS0_RTI_1_WDG_INTR_3 |
HSM0_NVIC_IN_176 | 176 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_136 |
HSM0_NVIC_IN_177 | 177 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_137 |
HSM0_NVIC_IN_178 | 178 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_138 |
HSM0_NVIC_IN_179 | 179 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_139 |
HSM0_NVIC_IN_180 | 180 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_140 |
HSM0_NVIC_IN_181 | 181 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_141 |
HSM0_NVIC_IN_182 | 182 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_142 |
HSM0_NVIC_IN_183 | 183 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_143 |
HSM0_NVIC_IN_184 | 184 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_144 |
HSM0_NVIC_IN_185 | 185 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_145 |
HSM0_NVIC_IN_186 | 186 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_146 |
HSM0_NVIC_IN_187 | 187 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_147 |
HSM0_NVIC_IN_188 | 188 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_148 |
HSM0_NVIC_IN_189 | 189 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_149 |
HSM0_NVIC_IN_190 | 190 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_150 |
HSM0_NVIC_IN_191 | 191 | DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_151 |
HSM0_NVIC_IN_192 | 192 | GLUELOGIC_MAINRESET_REQUEST_GLUE_MAIN_PORZ_SYNC_STRETCH_0 |
HSM0_NVIC_IN_193 | 193 | GLUELOGIC_MAINRESET_REQUEST_GLUE_MAIN_RESETZ_SYNC_STRETCH_0 |
HSM0_NVIC_IN_194 | 194 | C7X256V1_CLEC_DFT_PBIST_CPU_0 |
HSM0_NVIC_IN_195 | 195 | PBIST0_DFT_PBIST_CPU_0 |
HSM0_NVIC_IN_196 | 196 | WKUP_VTM0_THERM_LVL_GT_TH1_INTR_0 |
HSM0_NVIC_IN_197 | 197 | WKUP_VTM0_THERM_LVL_LT_TH0_INTR_0 |
HSM0_NVIC_IN_198 | 198 | WKUP_VTM0_THERM_LVL_GT_TH2_INTR_0 |
HSM0_NVIC_IN_199 | 199 | ESM0_ESM_INT_CFG_LVL_0 |
HSM0_NVIC_IN_200 | 200 | ESM0_ESM_INT_HI_LVL_0 |
HSM0_NVIC_IN_201 | 201 | ESM0_ESM_INT_LOW_LVL_0 |
HSM0_NVIC_IN_202 | 202 | CBASS_FW0_DEFAULT_ERR_INTR_0 |
HSM0_NVIC_IN_203 | 203 | GICSS0_GIC_PWR0_WAKE_REQUEST_0 |
HSM0_NVIC_IN_204 | 204 | GICSS0_GIC_PWR0_WAKE_REQUEST_1 |
HSM0_NVIC_IN_205 | 205 | DDR32SS0_DDRSS_PLL_FREQ_CHANGE_REQ_0 |
HSM0_NVIC_IN_206 | 206 | SA3_SS0_SA_UL_0_SA_UL_PKA_0 |
HSM0_NVIC_IN_207 | 207 | SA3_SS0_SA_UL_0_SA_UL_TRNG_0 |
HSM0_NVIC_IN_208 | 208 | MAIN_GPIOMUX_INTROUTER0_OUTP_0 |
HSM0_NVIC_IN_209 | 209 | MAIN_GPIOMUX_INTROUTER0_OUTP_1 |
HSM0_NVIC_IN_210 | 210 | MAIN_GPIOMUX_INTROUTER0_OUTP_2 |
HSM0_NVIC_IN_211 | 211 | MAIN_GPIOMUX_INTROUTER0_OUTP_3 |
HSM0_NVIC_IN_212 | 212 | MAIN_GPIOMUX_INTROUTER0_OUTP_4 |
HSM0_NVIC_IN_213 | 213 | MAIN_GPIOMUX_INTROUTER0_OUTP_5 |
HSM0_NVIC_IN_214 | 214 | MAIN_GPIOMUX_INTROUTER0_OUTP_6 |
HSM0_NVIC_IN_215 | 215 | MAIN_GPIOMUX_INTROUTER0_OUTP_7 |
HSM0_NVIC_IN_216 | 216 | SA3_SS0_INTAGGR_0_INTAGGR_VINTR_0 |
HSM0_NVIC_IN_217 | 217 | SA3_SS0_INTAGGR_0_INTAGGR_VINTR_1 |
HSM0_NVIC_IN_218 | 218 | SA3_SS0_INTAGGR_0_INTAGGR_VINTR_2 |
HSM0_NVIC_IN_219 | 219 | SA3_SS0_INTAGGR_0_INTAGGR_VINTR_3 |
HSM0_NVIC_IN_220 | 220 | GLUELOGIC_SOC_ACCESS_ERR_INTR_GLUE_OUT_0 |
HSM0_NVIC_IN_221 | 221 | GLUELOGICN_LBIST_DONE_GLUE_OUT_0 |
HSM0_NVIC_IN_222 | 222 | GICSS0_GIC_PWR0_WAKE_REQUEST_2 |
HSM0_NVIC_IN_223 | 223 | GICSS0_GIC_PWR0_WAKE_REQUEST_3 |
HSM0_NVIC_IN_224 | 224 | FSS0_OSPI_0_OSPI_LVL_INTR_0 |
HSM0_NVIC_IN_225 | 225 | GPU0_DFT_PBIST_CPU_0 |
HSM0_NVIC_IN_226 | 226 | PBIST3_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_CPU_0 |
HSM0_NVIC_IN_227 | 227 | FSS0_FSAS_0_OTFA_INTR_ERR_PEND_0 |
HSM0_NVIC_IN_228 | 228 | VPAC0_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_CPU_0 |
HSM0_NVIC_IN_229 | 229 | COMPUTE_CLUSTER0_PBIST_0_DFT_PBIST_CPU_0 |
HSM0_NVIC_IN_230 | 230 | MCU_PBIST0_DFT_PBIST_CPU_0 |
HSM0_NVIC_IN_231 | 231 | C7X256V0_CLEC_DFT_PBIST_CPU_0 |
HSM0_NVIC_IN_232 | 232 | PBIST1_DFT_PBIST_CPU_0 |
HSM0_NVIC_IN_233 | 233 | PBIST2_DFT_PBIST_CPU_0 |
HSM0_NVIC_IN_235 | 235 | WKUP_PBIST0_DFT_PBIST_CPU_0 |
HSM0_NVIC_IN_237 | 237 | SAM67_DMPAC_WRAP0_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_CPU_0 |
HSM0_NVIC_IN_238 | 238 | PSC0_PSC_ALLINT_0 |
HSM0_NVIC_IN_239 | 239 | WKUP_PSC0_PSC_ALLINT_0 |