SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Interrupt Input Line | Interrupt ID | Source Interrupt |
---|---|---|
ESM0_ESM_LVL_EVENT_IN_0 | 0 | CSI_RX_IF0_CSI_ERR_IRQ_0 |
ESM0_ESM_LVL_EVENT_IN_1 | 1 | ECC_AGGR0_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_2 | 2 | ECC_AGGR0_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_3 | 3 | CPSW0_ECC_SEC_PEND_0 |
ESM0_ESM_LVL_EVENT_IN_4 | 4 | SMS0_RAT_0_EXP_INTR_0 |
ESM0_ESM_LVL_EVENT_IN_5 | 5 | MSRAM8KX256E0_ECC_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_6 | 6 | MSRAM8KX256E0_ECC_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_7 | 7 | PLLFRACF2_SSMOD17_LOCKLOSS_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_8 | 8 | WKUP_PSRAMECC_8K0_ECC_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_9 | 9 | DMASS0_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_10 | 10 | DMASS0_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_11 | 11 | FSS0_OSPI_0_OSPI_ECC_CORR_LVL_INTR_0 |
ESM0_ESM_LVL_EVENT_IN_12 | 12 | GICSS0_ECC_AGGR_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_13 | 13 | WKUP_PSRAMECC_8K0_ECC_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_14 | 14 | SMS0_RAT_1_EXP_INTR_0 |
ESM0_ESM_LVL_EVENT_IN_15 | 15 | PDMA0_ECC_SEC_PEND_0 |
ESM0_ESM_LVL_EVENT_IN_16 | 16 | MCAN0_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_ESM_LVL_EVENT_IN_17 | 17 | PLLFRACF2_SSMOD5_LOCKLOSS_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_18 | 18 | PLLFRACF2_SSMOD7_LOCKLOSS_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_19 | 19 | PLLFRACF2_SSMOD6_LOCKLOSS_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_20 | 20 | WKUP_ECC_AGGR0_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_21 | 21 | WKUP_ECC_AGGR0_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_22 | 22 | PSC0_ECC_AGGR_0_FW_CH_BR_ECC_AGGR_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_23 | 23 | PSC0_ECC_AGGR_0_FW_CH_BR_ECC_AGGR_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_24 | 24 | A53SS0_ECC_ECCAGGR0_CORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_25 | 25 | A53SS0_ECC_ECCAGGR1_CORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_26 | 26 | A53SS0_ECC_ECCAGGR_COREPAC_CORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_27 | 27 | PLLFRACF2_SSMOD16_LOCKLOSS_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_28 | 28 | PDMA1_ECC_SEC_PEND_0 |
ESM0_ESM_LVL_EVENT_IN_29 | 29 | PSRAMECC0_ECC_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_30 | 30 | WKUP_R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_31 | 31 | CSI_RX_IF2_CSI_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_32 | 32 | USB0_HOST_SYSTEM_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_33 | 33 | USB1_HOST_SYSTEM_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_34 | 34 | MMCSD2_EMMCSDSS_RXMEM_CORR_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_35 | 35 | USB0_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_36 | 36 | MMCSD2_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_37 | 37 | WKUP_ESM0_ESM_INT_CFG_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_38 | 38 | WKUP_ESM0_ESM_INT_HI_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_39 | 39 | WKUP_ESM0_ESM_INT_LOW_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_40 | 40 | WKUP_R5FSS0_COMMON0_ECC_DE_TO_ESM_0_0 |
ESM0_ESM_LVL_EVENT_IN_41 | 41 | CSI_RX_IF3_CSI_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_42 | 42 | WKUP_R5FSS0_COMMON0_ECC_SE_TO_ESM_0_0 |
ESM0_ESM_LVL_EVENT_IN_43 | 43 | PLLFRACF2_SSMOD18_LOCKLOSS_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_44 | 44 | COMPUTE_CLUSTER0_PBIST_0_DFT_PBIST_SAFETY_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_45 | 45 | A53SS0_ECC_ECCAGGR2_CORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_46 | 46 | A53SS0_ECC_ECCAGGR2_UNCORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_47 | 47 | A53SS0_ECC_ECCAGGR3_CORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_48 | 48 | A53SS0_ECC_ECCAGGR3_UNCORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_49 | 49 | MMCSD2_EMMCSDSS_TXMEM_CORR_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_50 | 50 | SMS0_DMTIMER_0_INTR_PEND_0 |
ESM0_ESM_LVL_EVENT_IN_51 | 51 | SMS0_DMTIMER_1_INTR_PEND_0 |
ESM0_ESM_LVL_EVENT_IN_52 | 52 | SMS0_DMTIMER_2_INTR_PEND_0 |
ESM0_ESM_LVL_EVENT_IN_53 | 53 | SMS0_DMTIMER_3_INTR_PEND_0 |
ESM0_ESM_LVL_EVENT_IN_54 | 54 | MMCSD0_EMMCSS_RXMEM_CORR_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_55 | 55 | MMCSD0_EMMCSS_RXMEM_UNCORR_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_56 | 56 | MMCSD0_EMMCSS_TXMEM_CORR_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_57 | 57 | MMCSD0_EMMCSS_TXMEM_UNCORR_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_58 | 58 | MMCSD1_EMMCSDSS_RXMEM_CORR_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_59 | 59 | MMCSD1_EMMCSDSS_RXMEM_UNCORR_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_60 | 60 | MMCSD1_EMMCSDSS_TXMEM_CORR_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_61 | 61 | MMCSD1_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_62 | 62 | DMASS1_ECC_AGGR_0_ECC_UNCORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_63 | 63 | DMASS1_ECC_AGGR_0_ECC_CORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_64 | 64 | C7X256V1_CLEC_DFT_PBIST_SAFETY_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_65 | 65 | MMCSD2_EMMCSDSS_TXMEM_UNCORR_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_66 | 66 | CSI_RX_IF0_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_67 | 67 | CPSW0_ECC_DED_PEND_0 |
ESM0_ESM_LVL_EVENT_IN_68 | 68 | MCAN1_MCANSS_ECC_CORR_LVL_INT_0 |
ESM0_ESM_LVL_EVENT_IN_69 | 69 | MCAN1_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_ESM_LVL_EVENT_IN_70 | 70 | CSI_RX_IF0_CSI_FATAL_0 |
ESM0_ESM_LVL_EVENT_IN_71 | 71 | CSI_RX_IF0_CSI_NONFATAL_0 |
ESM0_ESM_LVL_EVENT_IN_72 | 72 | CSI_RX_IF0_CSI_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_73 | 73 | DCC7_INTR_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_74 | 74 | FSS0_OSPI_0_OSPI_ECC_UNCORR_LVL_INTR_0 |
ESM0_ESM_LVL_EVENT_IN_75 | 75 | GICSS0_ECC_AGGR_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_76 | 76 | PSC0_FW_0_FW_CH_BR_DEFAULT_EXP_0 |
ESM0_ESM_LVL_EVENT_IN_77 | 77 | CSI_RX_IF0_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_78 | 78 | MCAN0_MCANSS_ECC_UNCORR_LVL_INT_0 |
ESM0_ESM_LVL_EVENT_IN_79 | 79 | DCC6_INTR_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_80 | 80 | CBASS_CENTRAL2_DEFAULT_EXP_0 |
ESM0_ESM_LVL_EVENT_IN_81 | 81 | SMS0_RTI_1_WDG_INTR_0 |
ESM0_ESM_LVL_EVENT_IN_82 | 82 | SMS0_RTI_1_WDG_INTR_1 |
ESM0_ESM_LVL_EVENT_IN_83 | 83 | SMS0_RTI_1_WDG_INTR_2 |
ESM0_ESM_LVL_EVENT_IN_84 | 84 | SMS0_RTI_1_WDG_INTR_3 |
ESM0_ESM_LVL_EVENT_IN_85 | 85 | SMS0_RTI_1_WDG_INTR_4 |
ESM0_ESM_LVL_EVENT_IN_86 | 86 | CBASS0_DEFAULT_EXP_0 |
ESM0_ESM_LVL_EVENT_IN_87 | 87 | SMS0_RTI_0_WDG_INTR_0 |
ESM0_ESM_LVL_EVENT_IN_88 | 88 | PDMA0_ECC_DED_PEND_0 |
ESM0_ESM_LVL_EVENT_IN_89 | 89 | PDMA1_ECC_DED_PEND_0 |
ESM0_ESM_LVL_EVENT_IN_90 | 90 | PSRAMECC0_ECC_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_91 | 91 | WKUP_R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_92 | 92 | SMS0_RTI_0_WDG_INTR_1 |
ESM0_ESM_LVL_EVENT_IN_93 | 93 | A53SS0_ECC_ECCAGGR1_UNCORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_94 | 94 | A53SS0_ECC_ECCAGGR0_UNCORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_95 | 95 | A53SS0_ECC_ECCAGGR_COREPAC_UNCORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_96 | 96 | SMS0_RTI_0_WDG_INTR_2 |
ESM0_ESM_LVL_EVENT_IN_97 | 97 | SMS0_RTI_0_WDG_INTR_3 |
ESM0_ESM_LVL_EVENT_IN_98 | 98 | DFTSS0_DFT_SAFETY_123_0 |
ESM0_ESM_LVL_EVENT_IN_99 | 99 | DFTSS0_DFT_SAFETY_MULTI_0 |
ESM0_ESM_LVL_EVENT_IN_100 | 100 | DFTSS0_DFT_SAFETY_ONE_0 |
ESM0_ESM_LVL_EVENT_IN_101 | 101 | MCU_MCU0_VDD_CORE_GLDTC_STAT_THRESH_HI_FLAG_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_102 | 102 | MCU_MCU0_VDD_CORE_GLDTC_STAT_THRESH_LOW_FLAG_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_103 | 103 | SMS0_RTI_0_WDG_INTR_4 |
ESM0_ESM_LVL_EVENT_IN_104 | 104 | WKUP_ECC_AGGR1_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_105 | 105 | WKUP_ECC_AGGR1_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_106 | 106 | SAM67_DMPAC_WRAP0_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_SAFETY_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_108 | 108 | PSRAMECC1_ECC_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_109 | 109 | PSRAMECC1_ECC_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_110 | 110 | CBASS_IPCSS0_DEFAULT_EXP_0 |
ESM0_ESM_LVL_EVENT_IN_111 | 111 | USB0_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_112 | 112 | DCC0_INTR_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_113 | 113 | DCC1_INTR_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_114 | 114 | DCC2_INTR_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_115 | 115 | DCC3_INTR_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_116 | 116 | DCC4_INTR_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_117 | 117 | DCC5_INTR_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_118 | 118 | SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_DED_PEND_0 |
ESM0_ESM_LVL_EVENT_IN_119 | 119 | SA3_SS0_DMSS_ECCAGGR_0_DMSS_ECC_SEC_PEND_0 |
ESM0_ESM_LVL_EVENT_IN_120 | 120 | SA3_SS0_SA_UL_0_SA_UL_ECC_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_121 | 121 | SA3_SS0_SA_UL_0_SA_UL_ECC_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_122 | 122 | CSI_RX_IF1_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_123 | 123 | CSI_TX_IF0_CDNS_RAM_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_124 | 124 | WKUP_R5FSS0_CORE0_EXP_INTR_0 |
ESM0_ESM_LVL_EVENT_IN_125 | 125 | CSI_TX_IF0_CDNS_RAM_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_126 | 126 | CSI_TX_IF0_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_127 | 127 | CSI_TX_IF0_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_128 | 128 | PLLFRACF2_SSMOD0_LOCKLOSS_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_129 | 129 | PLLFRACF2_SSMOD1_LOCKLOSS_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_130 | 130 | PLLFRACF2_SSMOD2_LOCKLOSS_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_131 | 131 | PLLFRACF2_SSMOD8_LOCKLOSS_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_132 | 132 | PLLFRACF2_SSMOD12_LOCKLOSS_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_133 | 133 | PLLFRACF2_SSMOD15_LOCKLOSS_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_134 | 134 | MCU_PLLFRACF2_SSMOD0_LOCKLOSS_IPCFG_0 |
ESM0_ESM_LVL_EVENT_IN_135 | 135 | GLUELOGIC_HFOSC0_CLKLOSS_GLUE_REF_CLK_LOSS_DETECT_OUT_0 |
ESM0_ESM_LVL_EVENT_IN_136 | 136 | WKUP_VTM0_THERM_LVL_LT_TH0_INTR_0 |
ESM0_ESM_LVL_EVENT_IN_137 | 137 | WKUP_VTM0_THERM_LVL_GT_TH1_INTR_0 |
ESM0_ESM_LVL_EVENT_IN_138 | 138 | WKUP_VTM0_THERM_LVL_GT_TH2_INTR_0 |
ESM0_ESM_LVL_EVENT_IN_139 | 139 | WKUP_VTM0_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_140 | 140 | WKUP_VTM0_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_141 | 141 | FSS0_FSAS_0_ECC_INTR_ERR_PEND_0 |
ESM0_ESM_LVL_EVENT_IN_142 | 142 | DSS_DSI0_ECC_INTR_UNCORR_LEVEL_SYS_0 |
ESM0_ESM_LVL_EVENT_IN_143 | 143 | USB1_ASF_INT_FATAL_0 |
ESM0_ESM_LVL_EVENT_IN_144 | 144 | A53SS0_EXTERRIRQ_0 |
ESM0_ESM_LVL_EVENT_IN_145 | 145 | A53SS0_INTERRIRQ_0 |
ESM0_ESM_LVL_EVENT_IN_146 | 146 | USB1_A_ECC_AGGR_CORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_147 | 147 | USB1_A_ECC_AGGR_UNCORRECTED_ERR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_148 | 148 | PBIST3_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_SAFETY_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_149 | 149 | C7X256V0_CLEC_DFT_PBIST_SAFETY_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_150 | 150 | SMS0_HSM_ECC_AGGR_0_ECC_CORRECTED_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_151 | 151 | SMS0_HSM_ECC_AGGR_0_ECC_UNCORRECTED_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_152 | 152 | MCU_PBIST0_DFT_PBIST_SAFETY_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_153 | 153 | SMS0_TIFS_ECC_AGGR_0_ECC_CORRECTED_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_154 | 154 | SMS0_TIFS_ECC_AGGR_0_ECC_UNCORRECTED_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_155 | 155 | USB1_ASF_INT_NONFATAL_0 |
ESM0_ESM_LVL_EVENT_IN_156 | 156 | GPU0_DFT_PBIST_SAFETY_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_157 | 157 | PBIST0_DFT_PBIST_SAFETY_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_158 | 158 | WKUP_PBIST0_DFT_PBIST_SAFETY_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_159 | 159 | WKUP_PBIST1_DFT_PBIST_SAFETY_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_160 | 160 | C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_161 | 161 | C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_1 |
ESM0_ESM_LVL_EVENT_IN_162 | 162 | C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_2 |
ESM0_ESM_LVL_EVENT_IN_163 | 163 | C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_3 |
ESM0_ESM_LVL_EVENT_IN_164 | 164 | C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_4 |
ESM0_ESM_LVL_EVENT_IN_165 | 165 | C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_5 |
ESM0_ESM_LVL_EVENT_IN_166 | 166 | C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_6 |
ESM0_ESM_LVL_EVENT_IN_167 | 167 | C7X256V0_CLEC_ESM_EVENTS_OUT_LEVEL_7 |
ESM0_ESM_LVL_EVENT_IN_168 | 168 | VPAC0_ECC_INTR0_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_169 | 169 | VPAC0_ECC_INTR0_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_170 | 170 | VPAC0_ECC_INTR1_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_171 | 171 | VPAC0_ECC_INTR1_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_172 | 172 | VPAC0_ECC_INTR3_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_173 | 173 | VPAC0_ECC_INTR3_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_174 | 174 | DDR32SS0_DDRSS_DRAM_ECC_CORR_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_175 | 175 | DDR32SS0_DDRSS_DRAM_ECC_UNCORR_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_176 | 176 | DDR32SS0_DDRSS_V2A_OTHER_ERR_LVL_0 |
ESM0_ESM_LVL_EVENT_IN_177 | 177 | VPAC0_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_SAFETY_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_178 | 178 | DSS_DSI0_DSI_0_SAFETY_ERROR_FATAL_INTR_0 |
ESM0_ESM_LVL_EVENT_IN_179 | 179 | DSS_DSI0_DSI_0_SAFETY_ERROR_NONFATAL_INTR_0 |
ESM0_ESM_LVL_EVENT_IN_180 | 180 | PCIE0_PCIE_ECC0_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_181 | 181 | PCIE0_PCIE_ECC0_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_182 | 182 | PCIE0_PCIE_ECC1_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_183 | 183 | WKUP_CBASS0_DEFAULT_EXP_0 |
ESM0_ESM_LVL_EVENT_IN_184 | 184 | GPU0_GPU_SAFETY_IRQ_0 |
ESM0_ESM_LVL_EVENT_IN_185 | 185 | CSI_TX_IF0_CSI_NONFATAL_0 |
ESM0_ESM_LVL_EVENT_IN_186 | 186 | CSI_TX_IF0_CSI_FATAL_0 |
ESM0_ESM_LVL_EVENT_IN_187 | 187 | CSI_RX_IF1_CSI_NONFATAL_0 |
ESM0_ESM_LVL_EVENT_IN_188 | 188 | CSI_RX_IF1_CSI_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_189 | 189 | CSI_RX_IF1_CSI_FATAL_0 |
ESM0_ESM_LVL_EVENT_IN_190 | 190 | CSI_RX_IF1_CSI_ERR_IRQ_0 |
ESM0_ESM_LVL_EVENT_IN_191 | 191 | CSI_RX_IF1_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_192 | 192 | C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_193 | 193 | C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_1 |
ESM0_ESM_LVL_EVENT_IN_194 | 194 | C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_2 |
ESM0_ESM_LVL_EVENT_IN_195 | 195 | C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_3 |
ESM0_ESM_LVL_EVENT_IN_196 | 196 | C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_4 |
ESM0_ESM_LVL_EVENT_IN_197 | 197 | C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_5 |
ESM0_ESM_LVL_EVENT_IN_198 | 198 | C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_6 |
ESM0_ESM_LVL_EVENT_IN_199 | 199 | C7X256V1_CLEC_ESM_EVENTS_OUT_LEVEL_7 |
ESM0_ESM_LVL_EVENT_IN_200 | 200 | CSI_RX_IF2_CSI_FATAL_0 |
ESM0_ESM_LVL_EVENT_IN_201 | 201 | CSI_RX_IF2_CSI_NONFATAL_0 |
ESM0_ESM_LVL_EVENT_IN_204 | 204 | CSI_RX_IF3_CSI_FATAL_0 |
ESM0_ESM_LVL_EVENT_IN_205 | 205 | CSI_RX_IF3_CSI_NONFATAL_0 |
ESM0_ESM_LVL_EVENT_IN_206 | 206 | CSI_RX_IF2_CSI_ERR_IRQ_0 |
ESM0_ESM_LVL_EVENT_IN_207 | 207 | PBIST1_DFT_PBIST_SAFETY_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_208 | 208 | R5FSS0_CORE0_ECC_CORRECTED_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_209 | 209 | R5FSS0_CORE0_ECC_UNCORRECTED_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_210 | 210 | R5FSS0_CORE0_EXP_INTR_0 |
ESM0_ESM_LVL_EVENT_IN_211 | 211 | R5FSS0_COMMON0_ECC_DE_TO_ESM_0_0 |
ESM0_ESM_LVL_EVENT_IN_212 | 212 | R5FSS0_COMMON0_ECC_SE_TO_ESM_0_0 |
ESM0_ESM_LVL_EVENT_IN_213 | 213 | PBIST2_DFT_PBIST_SAFETY_ERROR_0 |
ESM0_ESM_LVL_EVENT_IN_214 | 214 | CSI_RX_IF2_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_215 | 215 | CSI_RX_IF2_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_216 | 216 | CSI_RX_IF3_CORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_217 | 217 | CSI_RX_IF3_UNCORR_LEVEL_0 |
ESM0_ESM_LVL_EVENT_IN_222 | 222 | CSI_RX_IF3_CSI_ERR_IRQ_0 |
ESM0_ESM_LVL_EVENT_IN_223 | 223 | DCC8_INTR_ERR_LEVEL_0 |
ESM0_ESM_PLS_EVENT0_IN_224 | 224 | RTI0_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT1_IN_224 | 224 | RTI0_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT2_IN_224 | 224 | RTI0_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT0_IN_225 | 225 | RTI1_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT1_IN_225 | 225 | RTI1_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT2_IN_225 | 225 | RTI1_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT0_IN_226 | 226 | C7X256V0_CLEC_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT1_IN_226 | 226 | C7X256V0_CLEC_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT2_IN_226 | 226 | C7X256V0_CLEC_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT0_IN_227 | 227 | WKUP_RTI0_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT1_IN_227 | 227 | WKUP_RTI0_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT2_IN_227 | 227 | WKUP_RTI0_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT0_IN_228 | 228 | PBIST0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT1_IN_228 | 228 | PBIST0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT2_IN_228 | 228 | PBIST0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT0_IN_229 | 229 | PBIST1_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT1_IN_229 | 229 | PBIST1_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT2_IN_229 | 229 | PBIST1_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT0_IN_230 | 230 | GICSS0_AXIM_ERR_0 |
ESM0_ESM_PLS_EVENT1_IN_230 | 230 | GICSS0_AXIM_ERR_0 |
ESM0_ESM_PLS_EVENT2_IN_230 | 230 | GICSS0_AXIM_ERR_0 |
ESM0_ESM_PLS_EVENT0_IN_231 | 231 | GICSS0_ECC_FATAL_0 |
ESM0_ESM_PLS_EVENT1_IN_231 | 231 | GICSS0_ECC_FATAL_0 |
ESM0_ESM_PLS_EVENT2_IN_231 | 231 | GICSS0_ECC_FATAL_0 |
ESM0_ESM_PLS_EVENT0_IN_232 | 232 | PBIST3_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT1_IN_232 | 232 | PBIST3_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT2_IN_232 | 232 | PBIST3_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT0_IN_233 | 233 | WKUP_PBIST1_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT1_IN_233 | 233 | WKUP_PBIST1_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT2_IN_233 | 233 | WKUP_PBIST1_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT0_IN_234 | 234 | WKUP_PBIST0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT1_IN_234 | 234 | WKUP_PBIST0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT2_IN_234 | 234 | WKUP_PBIST0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT0_IN_235 | 235 | MCU_PBIST0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT1_IN_235 | 235 | MCU_PBIST0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT2_IN_235 | 235 | MCU_PBIST0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT0_IN_236 | 236 | RTI4_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT1_IN_236 | 236 | RTI4_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT2_IN_236 | 236 | RTI4_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT0_IN_237 | 237 | VPAC0_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT1_IN_237 | 237 | VPAC0_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT2_IN_237 | 237 | VPAC0_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT0_IN_238 | 238 | GPU0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT1_IN_238 | 238 | GPU0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT2_IN_238 | 238 | GPU0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT0_IN_239 | 239 | RTI5_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT1_IN_239 | 239 | RTI5_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT2_IN_239 | 239 | RTI5_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT0_IN_240 | 240 | COMPUTE_CLUSTER0_PBIST_0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT1_IN_240 | 240 | COMPUTE_CLUSTER0_PBIST_0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT2_IN_240 | 240 | COMPUTE_CLUSTER0_PBIST_0_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT0_IN_241 | 241 | RTI2_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT1_IN_241 | 241 | RTI2_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT2_IN_241 | 241 | RTI2_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT0_IN_242 | 242 | RTI3_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT1_IN_242 | 242 | RTI3_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT2_IN_242 | 242 | RTI3_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT0_IN_243 | 243 | PBIST2_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT1_IN_243 | 243 | PBIST2_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT2_IN_243 | 243 | PBIST2_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT0_IN_244 | 244 | SAM67_DMPAC_WRAP0_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT1_IN_244 | 244 | SAM67_DMPAC_WRAP0_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT2_IN_244 | 244 | SAM67_DMPAC_WRAP0_K3_PBIST_8C28P_4BIT_WRAP__DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT0_IN_245 | 245 | C7X256V1_CLEC_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT1_IN_245 | 245 | C7X256V1_CLEC_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT2_IN_245 | 245 | C7X256V1_CLEC_DFT_PBIST_CPU_0 |
ESM0_ESM_PLS_EVENT0_IN_248 | 248 | RTI15_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT1_IN_248 | 248 | RTI15_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT2_IN_248 | 248 | RTI15_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT0_IN_249 | 249 | RTI8_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT1_IN_249 | 249 | RTI8_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT2_IN_249 | 249 | RTI8_INTR_WWD_0 |
ESM0_ESM_PLS_EVENT0_IN_250 | 250 | SAM67_DMPAC_WRAP0_ECC_CORRECTED_ERR_PULSE_0 |
ESM0_ESM_PLS_EVENT1_IN_250 | 250 | SAM67_DMPAC_WRAP0_ECC_CORRECTED_ERR_PULSE_0 |
ESM0_ESM_PLS_EVENT2_IN_250 | 250 | SAM67_DMPAC_WRAP0_ECC_CORRECTED_ERR_PULSE_0 |
ESM0_ESM_PLS_EVENT0_IN_251 | 251 | SAM67_DMPAC_WRAP0_ECC_UNCORRECTED_ERR_PULSE_0 |
ESM0_ESM_PLS_EVENT1_IN_251 | 251 | SAM67_DMPAC_WRAP0_ECC_UNCORRECTED_ERR_PULSE_0 |
ESM0_ESM_PLS_EVENT2_IN_251 | 251 | SAM67_DMPAC_WRAP0_ECC_UNCORRECTED_ERR_PULSE_0 |