SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Each VP output can be configured in BT.656 or BT.1120 mode. The following standards are not supported in BT.656 mode:
Unsupported formats when BT.1120 mode is used:
BT.656/BT.1120 modes use embedded EAV/SAV syncs.
Enabling BT.656 or BT.1120 format for a VP output is done by setting DSS0_VP_CONFIG[20] BT656ENABLE or [21] BT1120ENABLE register bit, respectively
It is not possible to enable BT.656 and BT.1120 mode simultaneously on the same output.
Figure 12-508 shows signal mapping on video port DATA[23:0] output data bus. Bits 9 to 0 are dedicated for BT.656 mode (10-bit). In BT.656 mode however, for compatibility with existing 8-bit interfaces, the two LSBs are ignored and only bits [9-2] are effectively used.
Figure 12-509 shows signal mapping on video port DATA[23:0] output data bus for BT.1120 mode. Bits [19-10] (CbCr) and [9-0] (Y) are used in 20-bit mode. Bits [19-12] (CbCr) and [9-2] (Y) are used in 16-bit mode (YCbCr422).
VP outputs support both interlace and progressive content in BT.656/BT.1120 modes. For more information on timings configuration, see Section 12.9.1.4.1.10.7, DISPC VP Timing Generator and Display Panel Settings.
In progressive BT.656/BT.1120 mode the maximum output resolution will be limited, as it requires two pixel clock cycles to send out one pixel.