SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The block diagram of PCIe subsystem is shown in Figure 12-92. The subsystem id comprised of these major components – the PCIe Core with AXI interfaces, bridges to connect to the system CBASS0 interconnect controller and target interfaces, bridges to connect the system CBASS0 configuration interfaces, additional logic to implement the Precision Time Measurement (PTM), user configuration and interrupt, and RAM to support the controller FIFOs.
Figure 12-92 also shows some example data flows in the PCIe subsystem, such as: