SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
After a channel has been set up it can begin to be used to transmit packets. Packet transmission involves the following steps:
The Host is made aware of one or more chunks of data in memory that need to be transmitted as a packet. This may involve directly sourcing data from the Host or it may involve data which has been forwarded from another data source in the system.
The Host allocates and populates a host packet descriptor. The host will initialize the following fields within the packet descriptor:
Descriptor Type (set to Host).
Packet Length indicating the total number of bytes that are to be read from all of the buffers for this packet.
Source Tag.
Destination Tag.
Packet Type.
Any protocol specific flags for the given packet type.
Buffer Pointer with the byte aligned address of the first chunk of buffer data.
Buffer Length with the number of bytes in the first chunk of buffer data.
The Next Descriptor Pointer with the 16-byte aligned address of the next descriptor in this packet. If this is the last chunk of data in the packet, this field must be set to zero.
Any protocol specific descriptor sections that are required for the given packet type or system configuration.
The Host allocates and populates host buffer descriptors as necessary to point to any remaining chunks of data that belong to this packet. The host will initialize the following fields within the host buffer descriptor:
Buffer Pointer with the byte aligned address of the given chunk of buffer data.
Buffer Length with the number of bytes in the given chunk of buffer data.
The Next Descriptor Pointer with the 16-byte aligned address of the next descriptor in this packet. If this is the last chunk of data in the packet, this field must be set to zero.
The Host writes queues the packet onto one of the Transmit Queues for the desired DMA channel. Channels may provide more than one Tx Queue (if more than 1 flow is provided) and may provide a particular prioritization policy between the queues. This behavior is application specific and is controlled by the DMA controller / scheduler implementation.
The PKTDMA internally generates a level sensitive status signal for the queue which indicates if any packets are currently pending. This level sensitive status line is sent to the hardware block which is responsible for scheduling DMA operations.
The PKTDMA Tx engine is eventually brought into context for the corresponding channel and begins to process the packet.
The PKTDMA reads the packet descriptor pointer from the memory mapped ring for that channel/flow.
The PKTDMA reads the packet descriptor from memory.
The PKTDMA empties each buffer in sequence by transmitting the contents in one or more block data moves. The size of these blocks is application specific. The PKTDMA module specification is intended to document the block size used by a given implementation. As each buffer is emptied, the PKTDMA will read the next buffer descriptor to obtain the pointer and size of the data buffer as well as the pointer to the next descriptor in the chain.
When all data for the packet has been transmitted as specified in the packet size field, the DMA will increment the occupancy of the reverse queue (Tx Completion Queue).
After the occupancy is incremented, the PKTDMA will indicate the status of the Tx Completion Queue by sending an up event.
The Interrupt Aggregator receives the up event and sets the corresponding bit in the interrupt status register (VINT[a]_STATUS_SET) as programmed in the interrupt mapping registers. This in turn causes an interrupt to the Host to be generated.
The Host responds to the status change from the PKTDMA (via the Interrupt Aggregator) and performs garbage collection as necessary for the packet.
During garbage collection the Host will write to the reverse queue Doorbell register (RINGRT[a]_RT_RDB) for the channel/flow to acknowledge the popping of those completed packets. The doorbell writes eventually cause the queue to become empty.
The PKTDMA will send a down event to the Interrupt Aggregator which will clear the corresponding bit in the Interrupt Status Register (VINT[a]_STATUS) and potentially de-assert the interrupt line.