SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The channel status registers (MCASP_DITCSRAi and MCASP_DITCSRBi) and user data registers (MCASP_DITUDRAi and MCASP_DITUDRBi) are not double-buffered. Typically, programmers use one of the synchronizing interrupts, such as the last slot, to create an event at a safe time so the register may be updated. In addition, the software reads the transmit TDM slot counter to determine which word of the register is being used (i = 0 to 5).
It is a software requirement to avoid writing to the word of user data and channel status that are being used to encode the current time slot; otherwise, it is undetermined whether old or new data is used to encode the bitstream.
The DIT subframe format is defined in Section 12.5.2.2.2.5.2, S/PDIF Subframe Format. The channel status information (C) and user data (U) are defined in the following DIT control registers:
The channel status and user data information sent on each subframe is summarized in Table 12-271.
Frame | Subframe | Preamble | Channel Status Defined in: | User Data Defined in: |
---|---|---|---|---|
Defined by DITCSRA0, DITCSRB0, DITUDRA0, DITUDRB0 | ||||
0 | 1 (L) | B | DITCSRA0[0] | DITUDRA0[0] |
0 | 2 (R) | W | DITCSRB0[0] | DITUDRB0[0] |
1 | 1 (L) | M | DITCSRA0[1] | DITUDRA0[1] |
1 | 2 (R) | W | DITCSRB0[1] | DITUDRB0[1] |
2 | 1 (L) | M | DITCSRA0[2] | DITUDRA0[2] |
2 | 2 (R) | W | DITCSRB0[2] | DITUDRB0[2] |
… | … | … | … | … |
31 | 1 (L) | M | DITCSRA0[31] | DITUDRA0[31] |
31 | 2 (R) | W | DITCSRB0[31] | DITUDRB0[31] |
Defined by DITCSRA1, DITCSRB1, DITUDRA1, DITUDRB1 | ||||
32 | 1 (L) | M | DITCSRA1[0] | DITUDRA1[0] |
32 | 2 (R) | W | DITCSRB1[0] | DITUDRB1[0] |
… | … | … | … | … |
63 | 1 (L) | M | DITCSRA1[31] | DITUDRA1[31] |
63 | 2 (R) | W | DITCSRB1[31] | DITUDRB1[31] |
Defined by DITCSRA2, DITCSRB2, DITUDRA2, DITUDRB2 | ||||
64 | 1 (L) | M | DITCSRA2[0] | DITUDRA2[0] |
64 | 2 (R) | W | DITCSRB2[0] | DITUDRB2[0] |
… | … | … | … | … |
95 | 1 (L) | M | DITCSRA2[31] | DITUDRA2[31] |
95 | 2 (R) | W | DITCSRB2[31] | DITUDRB2[31] |
Defined by DITCSRA3, DITCSRB3, DITUDRA3, DITUDRB3 | ||||
96 | 1 (L) | M | DITCSRA3[0] | DITUDRA3[0] |
96 | 2 (R) | W | DITCSRB3[0] | DITUDRB3[0] |
… | … | … | … | … |
127 | 1 (L) | M | DITCSRA3[31] | DITUDRA3[31] |
127 | 2 (R) | W | DITCSRB3[31] | DITUDRB3[31] |
Defined by DITCSRA4, DITCSRB4, DITUDRA4, DITUDRB4 | ||||
128 | 1 (L) | M | DITCSRA4[0] | DITUDRA4[0] |
128 | 2 (R) | W | DITCSRB4[0] | DITUDRB4[0] |
… | … | … | … | … |
159 | 1 (L) | M | DITCSRA4[31] | DITUDRA4[31] |
159 | 2 (R) | W | DITCSRB4[31] | DITUDRB4[31] |
Defined by DITCSRA5, DITCSRB5, DITUDRA5, DITUDRB5 | ||||
160 | 1 (L) | M | DITCSRA5[0] | DITUDRA5[0] |
160 | 2 (R) | W | DITCSRB5[0] | DITUDRB5[0] |
… | … | … | … | … |
191 | 1 (L) | M | DITCSRA5[31] | DITUDRA5[31] |
191 | 2 (R) | W | DITCSRB5[31] | DITUDRB5[31] |