SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The VBUSM2AXI bridge sets to 0x1 the EMIF_SSCFG_V2A_INT_RAW_REG[1] AERR bit, if the VBUSM address for an access that falls outside the DDR space programmed in the EMIF_SSCFG_V2A_CTL_REG register.
The VBUSM2AXI bridge sets to 0x1 the EMIF_SSCFG_V2A_INT_RAW_REG[2] TOERR bit, if it detects a hang on its interface to the DDR controller.
The VBUSM2AXI bridge sets to 0x1 the EMIF_SSCFG_V2A_INT_RAW_REG[3] ECC1BERR bit, if the threshold for 1-bit ECC errors is met.
The VBUSM2AXI bridge sets to 0x1 the EMIF_SSCFG_V2A_INT_RAW_REG[4] ECC2BERR bit, in case of 2-bit errors for a read access performed within the SDRAM address range protected by ECC.
The DDRSS0 asserts particular interrupt line only if the interrupts are enabled by writing 0x1 to the corresponding bit in the EMIF_SSCFG_V2A_INT_SET_REG register. The interrupts can be disabled by writing 0x1 to the corresponding bit in the EMIF_SSCFG_V2A_INT_CLR_REG register.
When interrupts are enabled, the corresponding bits in the EMIF_SSCFG_V2A_INT_STAT_REG register are also set if an interrupt condition occurs. The interrupts can be cleared once serviced by writing 0x1 to the corresponding bit in the EMIF_SSCFG_V2A_INT_STAT_REG register as well as writing to the EMIF_SSCFG_V2A_EOI_REG register. The subsystem will send an interrupt pulse, if there are any bits set in the Interrupt Status register (EMIF_SSCFG_V2A_INT_STAT_REG) when the End of Interrupt register (EMIF_SSCFG_V2A_EOI_REG) is written.
VBUSM2AXI Bridge Events shows the events that are generated by the VBUSM2AXI bridge.
Event Flag | Event Mask | Description |
---|---|---|
EMIF_SSCFG_V2A_INT_RAW_REG[4] ECC2BERR EMIF_SSCFG_V2A_INT_STAT_REG[4] ECC2BERR | EMIF_SSCFG_V2A_INT_SET_REG[4] ECC2BERR_EN EMIF_SSCFG_V2A_INT_CLR_REG[4] ECC2BERR_EN | Generated in case of 2-bit errors for a read access within the ECC protected SDRAM address range. For more information, see Section 9.1.3.4.3. |
EMIF_SSCFG_V2A_INT_RAW_REG[3] ECC1BERR EMIF_SSCFG_V2A_INT_STAT_REG[3] ECC1BERR | EMIF_SSCFG_V2A_INT_SET_REG[3] ECC1BERR_EN EMIF_SSCFG_V2A_INT_CLR_REG[3] ECC1BERR_EN | Generated in case of meeting the threshold for 1-bit ECC errors. For more information, see Section 9.1.3.4.3. |
EMIF_SSCFG_V2A_INT_RAW_REG[2] TOERR EMIF_SSCFG_V2A_INT_STAT_REG[2] TOERR | EMIF_SSCFG_V2A_INT_SET_REG[2] TOERR_EN EMIF_SSCFG_V2A_INT_CLR_REG[2] TOERR_EN | Generated in case of a hang of the interface between the bridge and the DDR controller. For more information, see Section 9.1.3.6. |
EMIF_SSCFG_V2A_INT_RAW_REG[1] AERR EMIF_SSCFG_V2A_INT_STAT_REG[1] AERR | EMIF_SSCFG_V2A_INT_SET_REG[1] AERR_EN EMIF_SSCFG_V2A_INT_CLR_REG[1] AERR_EN | Generated if the VBUSM address for an access falls outside the programmed range. For more information, see Section 9.1.3.5. |