The DPHY_TX0 module supports the
following main features:
- Compliance to MIPI D-PHY standard version 1.2.
- Supports up to 4 data lanes
and 1 clock lane.
- Supports High Speed up to 2.5
Gbps (with deskew) and 1.5 Gbps (without deskew) per data lane.
- Supports Escape mode:
- Remote triggers
- LP-DT up to 10
Mbps
- ULPS mode
- Clock Lane Control /
Interface Logic type is CIL-MCNN: [HS-TX, LP-TX]
- (M)
Controller
- Clock
- N/A forward,
N/A reverse escape mode features.
- Data Lane Control /
Interface Logic type is CIL-MFAA: [HS-TX, LP-TX,
LP-RX, LP-CD]
- (M)
Controller
- Forward
direction only for High Speed mode
- All forward
direction escape mode features are supported
- All reverse
direction escape mode features are supported.
- Data Lanes can be
independently operated in HS or ULP mode.
- Includes a CMN block with
reference generators / resistor calibration and an integrated PLL.
- Fault detection:
- Contention detection
(for example, when RX and TX sides of same link drive opposite LP
levels).
- Sequence error
detection (corruption on lanes).