SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Table 12-64 describes power-management features available for the UART.
For information about source clock gating and the sleep/wake-up transitions description, see Power in the Device Configuration.
Feature | Registers | Description |
---|---|---|
Clock autogating | UART_SYSC[0] AUTOIDLE | This bit allows local power optimization in the module by gating the clock on interface activity or gating the UARTi_FCLK clock on internal activity. |
Peripheral idle modes | UART_SYSC[4-3] IDLEMODE | Force-idle, no-idle, smart-idle, and smart-idle wakeup-capable modes are available. |
Clock activity | N/A | Feature not available |
Controller standby modes | N/A | Feature not available |
Global wake-up enable | UART_SYSC[2] ENAWAKEUP | This bit enables the wake-up feature at module level. |
Wake-Up sources enable | N/A | Feature not available |