SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Bits | Field | Type | Reset | Description |
---|---|---|---|---|
31:2 | addr | r/w | 0x0 |
This field contains the upper 30 bits of the32-bit interrupt vector address (addresses must be 32-bit aligned) of the currently pending highest priority IRQ (as indicated by the num field of the Prioritized IRQ (Base Address + 0x08). This field is only valid if the valid flag in the Prioritized IRQ (Base Address + 0x08) register is set.
|
1:0 | reserved | r/o | 0x0 | Reserved. Read as 0. The lower 2 bits of the 32-bit vector address are always 0. Vector addresses must be 32-bit aligned. |