The following apply to all or multiple boot
modes that are SPI related.
- Octal SPI flash memories support various protocols, however, the OSPI boot mode of the
device will only support a specific protocol defined in OSPI Bootloader Operation. If the
flash memory is complaint with JEDEC xSPI standards JESD251 and JESD216D, then xSPI boot
mode is additionally supported. Please refer to xSPI boot mode description for further
details.
- Command protocols follow the JEDEC spec definition and indicate the number of active
pins used for the instruction, address, and data, and also the data rate used for each (S
= Single Data Rate, D= Double Data Rate). For example, 1S-1S-8S describes a protocol
which uses 1 signal (D0) for command in SDR mode, 1 signal (D0) for address in SDR mode,
and 8 signals (D7:D0) for data in SDR mode
- When using a OSPI\xSPI\QSPI\SPI flash
device greater than 128Mb, a flash device package with a RESET signal must be used. The
reason is that the ROM only uses 3 byte addressing mode (address is 24bits). To address
the full memory address range, software will typically switch to 4-byte addressing mode.
If a reset to the processor occurs (eg, due to a warm reset), the ROM will execute
expecting 3-byte addressing mode, but the flash will have been left in 4-byte addressing
mode. In order for the flash device to return to 3-byte addressing mode, it must be reset
using this signal. This typically can be achieved by using the RESET signal on the flash
memory device. The ROM does not issue a software reset command.