The ARMv8 architecture spec requires specific system-level components, each with one or two register frames. To accommodate this, the GTC memory-mapped registers (MMRs) are divided into four separate regions (4KB each):
- Peripheral MMRs (GTC0_GTC_CFG0): This region
includes standard peripheral identification registers and any other control
registers not associated with the ARMv8 system timer functions.
- Counter control MMRs (GTC0_GTC_CFG1): This region
includes registers that provide control over the operation of the system
timer.
- Counter status MMRs (GTC0_GTC_CFG2): This region
includes registers that provide a mechanism for reading the status of the system
timer.
- Timer control MMRs (GTC0_GTC_CFG3): This region
includes registers that identify and provide a control mechanism for
memory-mapped timer implementations. For this device, no memory-mapped timers
are implemented and only the minimum registers required to indicate the presence
of no timers are necessary.