The VIM aggregates device interrupts and sends
them to the R5F CPU. It can be
used in either split or single-core configuration.
The VIM module supports the following features:
- 256 interrupt inputs for the R5F core
- Each interrupt has its own 4-bit programmable priority
- Defined via the R5FSS_VIM_PRI_INT_j register
- The VIM provides support for priority interruption of interrupts
- Each interrupt has its own enable mask
- Interrupt enable is done via the
R5FSS_VIM_INTR_EN_SET_j register
- Interrupt disable is done via the
R5FSS_VIM_INTR_EN_CLR_j register
- Each interrupt can be programmed as either an IRQ or FIQ
- Defined via the R5FSS_VIM_INTMAP_j register
- Each interrupt has its own programmable 32-bit vector address associated with it
- Defined via the R5FSS_VIM_VEC_INT_j register
- Protected with SECDED
- One IRQn and one FIQn output per core
- Vectored interrupt interface
- Compatible with R5F VIC port
- Default vector provided when a double-bit error is detected
- Software interrupt generation