SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The DSS0_COMMON_DSS_CBA_CFG register controls the priority level for DMA requests going out to the memory through the system interconnect.
As explained in Section 12.9.1.4.1.6.5, DISPC DMA MFLAG Mechanism, the DISPC Initiator port generates a 1-bit MFLAG output signal to raise the priority of all requests made on that port, if any of its DMA buffers runs critically low (determined by a set of user programmable threshold values for each buffer).
DSS uses the MFLAG signal from DISPC to set a 3-bit priority level output (Mpriority) for the Initiator port to either a low or high value (configurable in DSS0_COMMON_DSS_CBA_CFG[2-0] PRI_LO and [5-3] PRI_HI register fields with optional values of 0~7) as follows:
This Mpriority output directly drives the respective input of the system interconnect port, which corresponds to the DISPC DMA Initiator port.
Upon a hardware reset, DSS0_COMMON_DSS_CBA_CFG[2-0] PRI_LO and [5-3] PRI_HI register fields are set by default to 4 and 1, respectively. Afterwards, these priority level register fields can only be modified by a secure host.