The A53SS module supports the following features:
- Quad Core A53 Cluster
- Full Arm®v8-A Architecture Compliant
- AArch32 and
AArch64 Execution States
- All exception
levels EL0-3
- A32 Instruction
Set (Previously Arm instruction set)
- T32 instruction
set (Previously Thumb instruction set)
- A64 Instruction
Set
- Data Coherency within
Cluster (L1/L2 caches)
- Advanced SIMD and
Floating Point Extensions (Arm® Neon™)
- Armv8 Cryptography
Extensions
- Arm GICv3
architecture
- In-order pipeline with
symmetric dual-issue of most instructions
- Harvard L1 with system
MMU
- 32 KB Instruction
Cache
- 32 KB Data
Cache
- 512KB Shared L2
Cache
- Generic Timer(s)
- Debug
- 128-Bit VBUSM Initiator Interfaces (for axi_r and axi_r channels)
- 128-Bit VBUSM Target Interface (for Accelerator Coherency Port)
- 64-bit Grey-coded system input time
- 48-bit Grey-coded debug input time
- 48-bit Grey-coded debug input time
- Integrated PBIST controller with BISOR