SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
The RXx_FULL event is activated when a channel is enabled and the MCSPI_RXi register is being filled (transient event). When the FIFO buffer is enabled (the MCSPI_CHiCONF[28] FFER bit is set to 1), RXi_FULL is asserted as soon as the number of bytes held in the buffer to read defined by the MCSPI_XFERLEVEL[13-8] AFL bit field.
The MCSPI_RXi register must be read to remove the source of the interrupt; the MCSPI_IRQSTATUS RXi_FULL interrupt status bit must be cleared for interrupt line deassertion (if the event is enabled as the interrupt source).
When FIFO is enabled, no new RXi_FULL event is asserted as long as the processor has not performed AFL + 1 reads into MCSPI_RXi. The processor must perform the correct number of reads.