The CSI_RX module supports the following features:
- Fully Compliant to MIPI CSI v1.3 Specification
- Supports up to 16 virtual channels per input (partial support for MIPI CSI
v2.0)
- Data rate up to 2.5 Gbps per lane (wire rate)
- Supports 1, 2, 3, or 4 Data Lane connection to MIPI D-PHY
- Programmable formats including YUV420, YUV422, RGB, Raw, and User Defined (over
25 different formats supported)
- Four Independent (Simultaneous) Output Streams:
- Two VID32 streams to VISS inputs of VPAC Image Processing Accelerator
(2x 16-bit Pixels Per Clock)
- One (Up to 4 Channel) PPI 16-bit pixel Retransmission interface to
CSI-TX (2x 16-bit Pixels Per Clock)
- One (Up to 32 Channel) DMA interface through a 128 bit PSIL Connection
to NavSS/DMSS for transfers to memory.
- TI Wrapper Interrupts:
- PSIL fifo overflow
- VP0 frame/line mismatch
- VP1 frame/line mismatch
- CSI2-RX core functional (informational) interrupts:
- Stream Abort Process Complete (x4)
- Stream Stop Process Complete (x4)
- Reception of Generic Short Packet
- Reception of Short Packet
- Reception of Long Packet
- Deskew Entry
- ECC Spares Error (protocol non-compliance)
- D-PHY Sleep
- D-PHY Wakeup
- For stream 0, stream monitor interrupts:
- Line Count Error Interrupt
- Frame Mismatch Error Interrupt
- Frame Count Error Interrupt
- FCC Stop Interrupt
- FCC Start Interrupt
- Line/Byte Interrupt
- Timer / Timer Interrupt
- CSI Core / Datapath Error Interrupts:
- Stream FIFO Overflow (x4)
- Invalid Short Packet Received
- Invalid Access to Configuration Register Space
- Data ID Error in Packet Header
- Header ECC Error (Correctable/Uncorrectable)
- Payload CRC Error
- Front (D-PHY to CSI-RX) FIFO Overflow