SPRUJB3 March 2024 AM67 , AM67A , TDA4AEN-Q1 , TDA4VEN-Q1
Figure 12-97 shows the I/O interface signals of SERDES.
Although containing some of the basic external components, Figure 12-97 must not be considered as an exhaustive guide for the PCB designer. TI provides additional documents for those who are willing to design PCBs and/or fine tune the SerDes.
Table 12-118 describes the external signals of SERDES0 module.
Device Pin | Module Signal | I/O(1) | Description | Value at Reset |
---|---|---|---|---|
SERDES0_RX0_P | RX_P_LN0 | I | SerDes differential data receive pins | HiZ |
SERDES0_RX0_N | RX_M_LN0 | I | HiZ | |
SERDES0_TX0_P | TX_P_LN0 | O | SerDes differential data transmit pins | HiZ |
SERDES0_TX0_N | TX_M_LN0 | O | HiZ | |
SERDES0_REFCLK0P | CMN_REFCLK_P | I/O | SerDes external PCIe reference clock | HiZ |
SERDES0_REFCLK0N | CMN_REFCLK_N | I/O | HiZ | |
SERDES0_REXT | CMN_REXT | A/I | PMA external calibration resistor. Requires a 3.01 kOhm ±1% accurate off-chip resistor connected from this pin to ground. | HiZ |