SPRUJD8 June   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 Specification
  8. 2Hardware
    1. 2.1 Key Features and Interfaces
    2. 2.2 Power On/Off Procedure
    3. 2.3 Power Input
      1. 2.3.1 Power Supply
      2. 2.3.2 Power Control
      3. 2.3.3 Power Budget Considerations
    4. 2.4 User Inputs and Settings
      1. 2.4.1 Boot Configuration Settings
      2. 2.4.2 Board Configuration Settings
      3. 2.4.3 Reset Pushbuttons
      4. 2.4.4 User Pushbuttons
    5. 2.5 Standard Interfaces
      1. 2.5.1 Audio Input and Output
      2. 2.5.2 Display Port Interfaces
      3. 2.5.3 Gigabit Ethernet
      4. 2.5.4 JTAG/Emulation Interface
      5. 2.5.5 MicroSD Card Cage
      6. 2.5.6 PCIe Card Slot
      7. 2.5.7 UARTs for Terminal/Logging
      8. 2.5.8 USB Interface
    6. 2.6 Expansion Interfaces
      1. 2.6.1 Accessory Power Connector
      2. 2.6.2 Analog-to-Digital Conversion
      3. 2.6.3 Camera Interface
      4. 2.6.4 CAN-Bus Interface
      5. 2.6.5 Fan Header
      6. 2.6.6 LIN-Bus Interface
      7. 2.6.7 Test and Automation Control Interface
    7. 2.7 Circuit Details
      1. 2.7.1 Interface Mapping
      2. 2.7.2 Shared Interfaces / Signal Muxing
      3. 2.7.3 I2C Address Mapping
      4. 2.7.4 GPIO Mapping
      5. 2.7.5 Power Monitoring
      6. 2.7.6 Power Delivery Network (PDN)
      7. 2.7.7 Identification EEPROM
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  10. 4Compliance Information
    1. 4.1 EMC, EMI, and ESD Compliance
    2. 4.2 Reach Compliance
    3. 4.3 Thermal Compliance
  11. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
    2. 5.2 Trademarks

2.7.5 Power Monitoring

The EVM includes power monitoring and measurement capability for 32 discrete power rails, giving user critical power usage details for optimizing the processor application. The on-board analog-to-digital converters (INA226) are accessed via I2C. The processor can access using I2C1. The test automation [J50] can access the I2C bus, or can be accessed externally via 5-pin header [J30]. Due to the number of rails, the ADCs are split across two I2C buses. Selection of the buses is done via mux setting (see Section 2.7.4).

Table 2-22 Power Monitor Mapping
Bus #1 AddressPower RailNom VShunt ValueBus #2 AddressPower RailNom VShunt Value
0x40

Processor MCU VDD

(VDD_MCU_0V85)

0.85V10m-ohm0x40Processor IO at 1.8V (VDD_IO_1V8)1.8V10m-ohm
0x41

Processor MCU RAM

(VDD_MCU_RAM_0V85)

0.85V10m-ohm0x41Processor IO at 3.3V (VDD_IO_3V3)3.3V10m-ohm
0x42(VDA_MCU_1V8)1.8V10m-ohm0x42Processor Dual Voltage IO (VDD_SD_DV)DV10m-ohm
0x43

Processor MCU IO at 3.3V

(VDD_MCUIO_3V3)

3.3V10m-ohm0x43

LPDDR4 Memory (VDD1)

(VDD1_DDR_1V8)

1.8V10m-ohm
0x44

Processor MCU IO at 1.8V

(VDD_MCUIO_1V8)

1.8V10m-ohm0x44(VDD_DDR_SOC_1V1)1.1V
0x45(VDD_CORE_0V8)N/AN/A0x45(VCCA_3V3_CORE)3.3V5m-ohm
0x46(VDD_RAM_0V85)0.85V10m-ohm0x46

MCU Peripherals at 1.8V

(VSYS_MCUIO_1V8)

1.8V10m-ohm
0x47(VDD_GPIORET_WK_0V8)0.8V10m-ohm0x47

MCU Peripherals at 3.3V

(VSYS_MCUIO_3V3)

3.3V10m-ohm
0x48(VDD_CPU_AVS)N/AN/A0x48(VSYS_IO_1V8)1.8V10m-ohm
0x49(VSYS_GPIORET_IO_3V3)3.3V10m-ohm0x49(VSYS_IO_3V3)3.3V10m-ohm
0x4A

Processor LPDDR IO

(VDD_DDR_1V1)

N/AN/A0x4A(VCC_12V0_N)12V??m-Ohm
0x4B(VDD_PHYCORE_0V8)0.8V10m-ohm0x4B(VSYS_5V0)5V0
0x4C(VDA_PLL_1V8)1.8V10m-ohm0x4C(VSYS_3V3)3V3
0x4D(VDA_PHY_1V8)1.8V10m-ohm0x4D(VCCA_3V3_DDR)3.3V10m-ohm
0x4E(VDA_USB_3V3)3.3V10m-ohm0x4E(VDA_DLL_0V8)0.8V10m-ohm
0x4F(VDD_GPIORET_IO_3V3)3.3V10m-ohm0x4F(VCCA_3V3_CPU_AVS)3.3V5m-ohm
Note: In the table, the ‘(_name)’ refers to the net name used in the schematic.