SPRUJD8 June   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 Specification
  8. 2Hardware
    1. 2.1 Key Features and Interfaces
    2. 2.2 Power On/Off Procedure
    3. 2.3 Power Input
      1. 2.3.1 Power Supply
      2. 2.3.2 Power Control
      3. 2.3.3 Power Budget Considerations
    4. 2.4 User Inputs and Settings
      1. 2.4.1 Boot Configuration Settings
      2. 2.4.2 Board Configuration Settings
      3. 2.4.3 Reset Pushbuttons
      4. 2.4.4 User Pushbuttons
    5. 2.5 Standard Interfaces
      1. 2.5.1 Audio Input and Output
      2. 2.5.2 Display Port Interfaces
      3. 2.5.3 Gigabit Ethernet
      4. 2.5.4 JTAG/Emulation Interface
      5. 2.5.5 MicroSD Card Cage
      6. 2.5.6 PCIe Card Slot
      7. 2.5.7 UARTs for Terminal/Logging
      8. 2.5.8 USB Interface
    6. 2.6 Expansion Interfaces
      1. 2.6.1 Accessory Power Connector
      2. 2.6.2 Analog-to-Digital Conversion
      3. 2.6.3 Camera Interface
      4. 2.6.4 CAN-Bus Interface
      5. 2.6.5 Fan Header
      6. 2.6.6 LIN-Bus Interface
      7. 2.6.7 Test and Automation Control Interface
    7. 2.7 Circuit Details
      1. 2.7.1 Interface Mapping
      2. 2.7.2 Shared Interfaces / Signal Muxing
      3. 2.7.3 I2C Address Mapping
      4. 2.7.4 GPIO Mapping
      5. 2.7.5 Power Monitoring
      6. 2.7.6 Power Delivery Network (PDN)
      7. 2.7.7 Identification EEPROM
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  10. 4Compliance Information
    1. 4.1 EMC, EMI, and ESD Compliance
    2. 4.2 Reach Compliance
    3. 4.3 Thermal Compliance
  11. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
    2. 5.2 Trademarks

Camera Interface

The EVM includes dual 40-pin (2x20, 0.5mm pitch) high speed connectors [J57] [J55] for connecting with cameras and other image capture devices. Each expansion connectors can support up to two MIPI-DPHY CSI2 interfaces. The bandwidth of each CSI2 interface is 10Gbps (each CSI2 port supports 4 data lanes each lanes up to 2.5Gbps). The expansion connectors also includes power and other IO for communicating with the capture devices. All control signals are configurable for 3.3V or 1.8V IO voltage levels. See Section 2.4.1 for configuration details.

Table 2-12 High Speed Camera Expansion Pin Definition [J57][J55]
Pin #Pin NameDescription Processor Resource for [J57] / [J55]Dir
1PowerPower, 12VOutput
2I2C_SCLI2C Bus Clock (I2C5)Bi-Dir
3PowerPower, 12VOutput
4I2C_SDAI2C Bus Data (I2C5)Bi-Dir
5CSIa_CLK_PCSI Port 0 / Port 2Input
6GPIO0/PWMAIO Expander 0x20 bit P1 / OpenOutput
7CSIa_CLK_NCSI Port 0 / Port 2Input
8GPIO1/PWMVIO Expander 0x20 bit P2 / bit P4Bi-Dir
9CSIa_D0_PCSI Port 0 / Port 2Input
10REFCLK25MHz Reference ClockOutput
11CSIa_D0_NCSI Port 0 / Port 2Input
12GNDGround
13CSIa_D1_PCSI Port 0 / Port 2Input
14RESETzGPIO, IO Expander 0x20 bit P0Output
15CSIa_D1_NCSI Port 0 / Port 2Input
16GNDGround
17CSIa_D2_PCSI Port 0 / Port 2Input
18GPIO2GPIO0_26 / IO Expander 0x20 bit P5Bi-Dir
19CSIa_D2_NCSI Port 0 / Port 2Input
20GPIO3IO Expander 0x20 bit P3 / bit P6Bi-Dir
21CSIa_D3_PCSI Port 0 / Port 2Input
22GPIO4GPIO0_28 / IO Expander 0x20 bit P7Bi-Dir
23CSIa_D3_NCSI Port 0 / Port 2Input
24GNDGround
25CSIb_CLK_PCSI Port 1 / OpenInput
26CSIb_D3_PCSI Port 1 / OpenInput
27CSIb_CLK_NCSI Port 1 / OpenInput
28CSIb_D3_NCSI Port 1 / OpenInput
29CSIb_D0_PCSI Port 1 / OpenInput
30PowerPower, 3.3VOutput
31CSIb_D0_NCSI Port 1 / OpenInput
32PowerPower, 3.3VOutput
33CSIb_D1_PCSI Port 1 / OpenInput
34PowerPower, 3.3VOutput
35CSIb_D1_NCSI Port 1 / OpenInput
36PowerPower, 3.3VOutput
37CSIb_D2_PCSI Port 1 / OpenInput
38PowerPower, IO Level (1.8V or 3.3V)Output
39CSIb_D2_NCSI Port 1 / OpenInput
40PowerPower, IO Level (1.8V or 3.3V)Output