SPRUJD8 June   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 Specification
  8. 2Hardware
    1. 2.1 Key Features and Interfaces
    2. 2.2 Power On/Off Procedure
    3. 2.3 Power Input
      1. 2.3.1 Power Supply
      2. 2.3.2 Power Control
      3. 2.3.3 Power Budget Considerations
    4. 2.4 User Inputs and Settings
      1. 2.4.1 Boot Configuration Settings
      2. 2.4.2 Board Configuration Settings
      3. 2.4.3 Reset Pushbuttons
      4. 2.4.4 User Pushbuttons
    5. 2.5 Standard Interfaces
      1. 2.5.1 Audio Input and Output
      2. 2.5.2 Display Port Interfaces
      3. 2.5.3 Gigabit Ethernet
      4. 2.5.4 JTAG/Emulation Interface
      5. 2.5.5 MicroSD Card Cage
      6. 2.5.6 PCIe Card Slot
      7. 2.5.7 UARTs for Terminal/Logging
      8. 2.5.8 USB Interface
    6. 2.6 Expansion Interfaces
      1. 2.6.1 Accessory Power Connector
      2. 2.6.2 Analog-to-Digital Conversion
      3. 2.6.3 Camera Interface
      4. 2.6.4 CAN-Bus Interface
      5. 2.6.5 Fan Header
      6. 2.6.6 LIN-Bus Interface
      7. 2.6.7 Test and Automation Control Interface
    7. 2.7 Circuit Details
      1. 2.7.1 Interface Mapping
      2. 2.7.2 Shared Interfaces / Signal Muxing
      3. 2.7.3 I2C Address Mapping
      4. 2.7.4 GPIO Mapping
      5. 2.7.5 Power Monitoring
      6. 2.7.6 Power Delivery Network (PDN)
      7. 2.7.7 Identification EEPROM
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  10. 4Compliance Information
    1. 4.1 EMC, EMI, and ESD Compliance
    2. 4.2 Reach Compliance
    3. 4.3 Thermal Compliance
  11. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
    2. 5.2 Trademarks

2.1 Key Features and Interfaces

The J742S2XH01EVM is a high performance, standalone development platform that enables users to evaluate and develop automotive and industrial applications using the Texas Instruments' J742S2/TDA4VPE/TDA4APE processor. A summary of the EVM features include:

  • Processor (also referred to as SoC or System-on-Chip):
    • Texas Instruments' Jacinto J742S2 super-set device
  • Optimized power management design:
    • Dynamic voltage scaling
    • Multiple clock and power domains
    • Multiple low power/sleep modes (MCU only, IO retention)
  • Memory:
    • 16GB LPDDR4 DRAM (4266 MT/s), support inline ECC
    • Two 512Mb non-volatile NOR Memories, 1x Octal-SPI and 1x Quad-SPI
    • 1Gb non-volatile NAND Memory, Octal-SPI
    • 32GB non-volatile eMMC Memory, JEDEC/MMC v5.1 compliant
    • 32GB non-volatile UFS Memory, 2Lane, Gear3
    • Multimedia card (MMC)/secure digital card (Micro-SD) cage, UHS‐1
  • USB:
    • USB3.1 (Gen 1) Type C interface, support DFP, DRP, UFP modes
    • USB2.0 Hub to 2x Type A (host), 1x pin header for PCIe WiFi® support
    • Two USB2.0 Micro B (for dual/quad UART-over-USB transceiver)
  • Display:
    • VESA DisplayPort (v1.4), supports 4K UHD with MST support
    • VESA DisplayPort (v1.4), supports 2K QHD
    • Custom CSI2-TX expansion interface
  • Wired network:
    • Two gigabit Ethernet (RJ45 connector)
    • Six CAN-FD interfaces
    • Two LIN interfaces
  • Camera:
    • Three CSI2-RX camera interfaces (custom interface/dual-QSH connectors)
  • Audio:
    • 3.5mm stereo input and output
  • Expansion/add-on:
    • Two PCIe/Gen3 4L card slots (1x with 4Lane support, 1x with 2L support)
    • Multiple pin headers for ADC, I2C, I3C, and SPI access
  • User control/indication:
    • Pushbuttons (resets, power modes, user defined)
    • LEDs (power, user defined, serial port)
    • User configurations (boot mode, USB mode)
    • External or onboard emulator support (MIPI-60 w/ adapters to 14-pin or 20-pin CTI)

The EVM images identify the locations of these key features and user interfaces (top and bottom view).

J742S2XH01EVM Key Features and Interfaces (Top) Figure 2-1 Key Features and Interfaces (Top)
J742S2XH01EVM Key Features and Interfaces (Bottom) Figure 2-2 Key Features and Interfaces (Bottom)