SPRUJD8 June   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 Specification
  8. 2Hardware
    1. 2.1 Key Features and Interfaces
    2. 2.2 Power On/Off Procedure
    3. 2.3 Power Input
      1. 2.3.1 Power Supply
      2. 2.3.2 Power Control
      3. 2.3.3 Power Budget Considerations
    4. 2.4 User Inputs and Settings
      1. 2.4.1 Boot Configuration Settings
      2. 2.4.2 Board Configuration Settings
      3. 2.4.3 Reset Pushbuttons
      4. 2.4.4 User Pushbuttons
    5. 2.5 Standard Interfaces
      1. 2.5.1 Audio Input and Output
      2. 2.5.2 Display Port Interfaces
      3. 2.5.3 Gigabit Ethernet
      4. 2.5.4 JTAG/Emulation Interface
      5. 2.5.5 MicroSD Card Cage
      6. 2.5.6 PCIe Card Slot
      7. 2.5.7 UARTs for Terminal/Logging
      8. 2.5.8 USB Interface
    6. 2.6 Expansion Interfaces
      1. 2.6.1 Accessory Power Connector
      2. 2.6.2 Analog-to-Digital Conversion
      3. 2.6.3 Camera Interface
      4. 2.6.4 CAN-Bus Interface
      5. 2.6.5 Fan Header
      6. 2.6.6 LIN-Bus Interface
      7. 2.6.7 Test and Automation Control Interface
    7. 2.7 Circuit Details
      1. 2.7.1 Interface Mapping
      2. 2.7.2 Shared Interfaces / Signal Muxing
      3. 2.7.3 I2C Address Mapping
      4. 2.7.4 GPIO Mapping
      5. 2.7.5 Power Monitoring
      6. 2.7.6 Power Delivery Network (PDN)
      7. 2.7.7 Identification EEPROM
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  10. 4Compliance Information
    1. 4.1 EMC, EMI, and ESD Compliance
    2. 4.2 Reach Compliance
    3. 4.3 Thermal Compliance
  11. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
    2. 5.2 Trademarks

1.1 Introduction

The J742S2XH01EVM is a standalone test, development, and evaluation module that contains a variety of both on-board peripherals and external interfaces, giving customers the flexibility to customize the platform to their needs. This design is not a reference design, as the design includes circuity for software development/debug and configuration flexibility. However, some portions of the design are optimized and can be considered as reference (LPDDR4 implementation as an example). The J742S2XH01EVM EVM supports multiple feature-rich software development kits (SDK) not covered in this user’s guide. This document describes how to use the hardware as well as some of the architecture and design elements of the EVM.

The TDA4VPE-Q1 and TDA4APE-Q1 processors have a powerful heterogeneous architecture that includes a mix of DSP cores, Arm Cortex-A72 cores, matrix math acceleration for artificial intelligence (AI), integrated image signal processor (ISP) and vision-processing acceleration, 3D graphics processing unit (GPU) cores, and H.264 and H.265 encode and decode acceleration. An integrated safety microcontroller unit (MCU) includes dual-lockstep Arm Cortex-R5F cores that aid the system in achieving ASIL-D-level certification.

The EVM allows for multicamera inpust via CSI-2 ports and multi-display connectivity via the DisplayPort and display serial interface (DSI). Connectivity includes a USB3.1 Gen 1 (Dual role) Type C interface, two PCI-Express (Gen3) card interfaces, dual Gigabit Ethernet® interfaces, multiple CAN Bus interfaces with CAN-FD support, onboard XDS110 Joint Action Group (JTAG) emulator, and six universal asynchronous receiver-transmitters (UARTs) via USB2.0-B.