SPRUJD8 June   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 Specification
  8. 2Hardware
    1. 2.1 Key Features and Interfaces
    2. 2.2 Power On/Off Procedure
    3. 2.3 Power Input
      1. 2.3.1 Power Supply
      2. 2.3.2 Power Control
      3. 2.3.3 Power Budget Considerations
    4. 2.4 User Inputs and Settings
      1. 2.4.1 Boot Configuration Settings
      2. 2.4.2 Board Configuration Settings
      3. 2.4.3 Reset Pushbuttons
      4. 2.4.4 User Pushbuttons
    5. 2.5 Standard Interfaces
      1. 2.5.1 Audio Input and Output
      2. 2.5.2 Display Port Interfaces
      3. 2.5.3 Gigabit Ethernet
      4. 2.5.4 JTAG/Emulation Interface
      5. 2.5.5 MicroSD Card Cage
      6. 2.5.6 PCIe Card Slot
      7. 2.5.7 UARTs for Terminal/Logging
      8. 2.5.8 USB Interface
    6. 2.6 Expansion Interfaces
      1. 2.6.1 Accessory Power Connector
      2. 2.6.2 Analog-to-Digital Conversion
      3. 2.6.3 Camera Interface
      4. 2.6.4 CAN-Bus Interface
      5. 2.6.5 Fan Header
      6. 2.6.6 LIN-Bus Interface
      7. 2.6.7 Test and Automation Control Interface
    7. 2.7 Circuit Details
      1. 2.7.1 Interface Mapping
      2. 2.7.2 Shared Interfaces / Signal Muxing
      3. 2.7.3 I2C Address Mapping
      4. 2.7.4 GPIO Mapping
      5. 2.7.5 Power Monitoring
      6. 2.7.6 Power Delivery Network (PDN)
      7. 2.7.7 Identification EEPROM
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  10. 4Compliance Information
    1. 4.1 EMC, EMI, and ESD Compliance
    2. 4.2 Reach Compliance
    3. 4.3 Thermal Compliance
  11. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
    2. 5.2 Trademarks

2.7.7 Identification EEPROM

The EVM board identity and revision information are stored in an onboard EEPROM. The first 259 bytes of the memory are preprogrammed with EVM identification information. The format of that data is provided in the table below. The remaining 32509 bytes are available for data or code storage.

The EEPROM is accessible from WKUP I2C0 port of processor at address 0x51.

Table 2-23 Board ID Memory Header Information
Field NameOffset /SizeValueComments
MAGIC0000 / 4B (Hex)0xEE3355AAHeader Identifier
M_TYPE0004 / 1B (Hex)0x1Fixed length and variable position board ID header
M_LENGTH0005 / 2B (Hex)0x10BSize of payload
B_TYPE0007 / 1B (Hex)0x10Payload type
B_LENGTH0008 / 2B (Hex)0x2EOffset to next header
B_NAME000A / 16B (CHAR)J742S2X-EVMName of the board
DESGIN_REV001A / 2B (CHAR)E1Revision number of the design
PROC_NBR001C / 4B (CHAR)184PROC number
VARIANT0020 / 2B (CHAR)

2

Design variant number
PCB_REV0022 / 2B (CHAR)E1Revision number of the PCB
SCHBOM_REV0024 / 2B (CHAR)0Revision number of the schematic
SWR_REV0026 / 2B (CHAR)1first software release number
VENDORID0028 / 2B (CHAR)10x1: Manufactured by Mistral
BUILD_WK002A / 2B (CHAR)week of the year of production
BUILD_YR002C / 2B (CHAR)year of production
BOARDID002E / 6B (CHAR)0
SERIAL_NBR0034 / 4B (CHAR)4incrementing board number
DDR_TYPE0038 / 1B (Hex)0x11DDR Header Identifier
DDR_LENGTH0039 / 2B (Hex)0x2offset to next header
DDR_CONTROL003B / 2B (Hex)0xC560

DDR Control Word

Bit 1:0 = ‘00’ First DDR

Bit 3:2 = ‘00’ No SPD

Bit 5:4 = ‘10’ LPDDR4

Bit 7:6 = ‘01’ 32 bits

Bit 9:8 = ‘01’ 32 bits

Bit 10 = ‘1’ dual rank

Bit 13:11 = ‘000’ Density 64 Gb(bit 0 to 3)

Bit 14 = ‘1’ ECC bits present (inline, not separate bits)

Bit 15 = ‘1’ Density 64 Gb (bit 4)

DDR_TYPE003D / 1B (Hex)0x11DDR Header Identifier
DDR_LENGTH003E / 2B (Hex)0x2offset to next header
DDR_CONTROL0040 / 2B (Hex)0xC561DDR Control Word)
MAC_TYPE0042 / 1B (Hex)0x13MAC address Header Identifier
MAC_LENGTH0043 / 2B (Hex)0xC2Size of payload
MAC_CONTROL0045 / 1B (Hex)0x0MAC header control word (0 = 1 MAC address)
MAC_ADDRS0047 / 192B (Hex)MAC address
END_LIST0107 / 1B (Hex)0xFEEnd Marker