SPRUJD8 June   2024

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Device Information
    4. 1.4 Specification
  8. 2Hardware
    1. 2.1 Key Features and Interfaces
    2. 2.2 Power On/Off Procedure
    3. 2.3 Power Input
      1. 2.3.1 Power Supply
      2. 2.3.2 Power Control
      3. 2.3.3 Power Budget Considerations
    4. 2.4 User Inputs and Settings
      1. 2.4.1 Boot Configuration Settings
      2. 2.4.2 Board Configuration Settings
      3. 2.4.3 Reset Pushbuttons
      4. 2.4.4 User Pushbuttons
    5. 2.5 Standard Interfaces
      1. 2.5.1 Audio Input and Output
      2. 2.5.2 Display Port Interfaces
      3. 2.5.3 Gigabit Ethernet
      4. 2.5.4 JTAG/Emulation Interface
      5. 2.5.5 MicroSD Card Cage
      6. 2.5.6 PCIe Card Slot
      7. 2.5.7 UARTs for Terminal/Logging
      8. 2.5.8 USB Interface
    6. 2.6 Expansion Interfaces
      1. 2.6.1 Accessory Power Connector
      2. 2.6.2 Analog-to-Digital Conversion
      3. 2.6.3 Camera Interface
      4. 2.6.4 CAN-Bus Interface
      5. 2.6.5 Fan Header
      6. 2.6.6 LIN-Bus Interface
      7. 2.6.7 Test and Automation Control Interface
    7. 2.7 Circuit Details
      1. 2.7.1 Interface Mapping
      2. 2.7.2 Shared Interfaces / Signal Muxing
      3. 2.7.3 I2C Address Mapping
      4. 2.7.4 GPIO Mapping
      5. 2.7.5 Power Monitoring
      6. 2.7.6 Power Delivery Network (PDN)
      7. 2.7.7 Identification EEPROM
  9. 3Hardware Design Files
    1. 3.1 Schematics
    2. 3.2 PCB Layouts
    3. 3.3 Bill of Materials (BOM)
  10. 4Compliance Information
    1. 4.1 EMC, EMI, and ESD Compliance
    2. 4.2 Reach Compliance
    3. 4.3 Thermal Compliance
  11. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
    2. 5.2 Trademarks

Test and Automation Control Interface

The EVM supports an interface to allow for automated control of the system, including functions like on/off, reset, and boot mode settings.

Table 2-17 Test Automation Interface Pin Definition [J50]
Pin #Pin NameDescriptionDir
1PowerPower, 3.3VOutput
2PowerPower, 3.3VOutput
3PowerPower, 3.3VOutput
4-6<open>
7GNDGround
8-15<open>
16GNDGround
17-24<open>
25GNDGround
26POWERDOWNzEVM Power DownInput
27PORzEVM Power-On/Cold Reset (MCU_PORz)Input
28RESETzEVM Warm Reset (RESETz)Input
29<open>
30INT1zEXTINT / GPIO0_0Input
31INT2zWKUP_GPIO0_7Bi-Dir
32<open>
33BOOTMODE_RSTzBootmode Buffer ResetInput
34GNDGround
35<open>
36Bus #1 I2C_SCLINA Bus #1 I2C (optional connection to Processor I2C1)Bi-Dir
37Bus #2 I2C_SCLINA Bus #2 I2CInput
38Bus #1 I2C_SDAINA Bus #1 I2C (optional connection to Processor I2C1)Bi-Dir
39Bus #2 I2C_SDAINA Bus #2 I2CBi-Dir
40GNDGround
41GNDGround
42GNDGround
Note: The Signal polarity is defined with a trailing 'z' in the Pin Name, which indicates the signal is active LOW. For example, POWERDOWNz is an active low signal, meaning '0' = EVM is Powered Down, '1' = EVM is NOT Powered Down.