SPRUJG2 December   2024 AM62D-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 EVM Revisions and Assembly Variants
  7. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Key Features
      1. 2.2.1 Processor
      2. 2.2.2 Power Supply
      3. 2.2.3 Memory
      4. 2.2.4 JTAG/Emulator
      5. 2.2.5 Supported Interfaces and Peripherals
      6. 2.2.6 Expansion Connectors/Headers to Support Application Specific Add‐On Boards
    3. 2.3  Power Requirement
    4. 2.4  Setup and Configuration
      1. 2.4.1 EVM DIP Switches
      2. 2.4.2 Boot modes
      3. 2.4.3 User Test LEDs
    5. 2.5  Power ON/OFF Procedures
      1. 2.5.1 Power ON Procedure
      2. 2.5.2 Power OFF Procedure
      3. 2.5.3 Power Test Points
    6. 2.6  Interfaces
      1. 2.6.1  AM62D Audio EVM Interface Mapping
      2. 2.6.2  Audio Interface
        1. 2.6.2.1 Audio Stereo Lineouts
        2. 2.6.2.2 Audio Microphone / Line In
      3. 2.6.3  JTAG Interface
      4. 2.6.4  UART Interface
      5. 2.6.5  USB Interface
        1. 2.6.5.1 USB2.0 Type-A Interface
        2. 2.6.5.2 USB2.0 Type-C Interface
      6. 2.6.6  MCAN Interface
      7. 2.6.7  Memory Interfaces
        1. 2.6.7.1 LPDDR4 Interface
        2. 2.6.7.2 Octal Serial Peripheral Interface (OSPI)
        3. 2.6.7.3 MMC Interfaces
          1. 2.6.7.3.1 MMC0 - eMMC Interface
          2. 2.6.7.3.2 MMC1 - MicroSD Interface
        4. 2.6.7.4 Board ID EEPROM
      8. 2.6.8  Ethernet Interface
      9. 2.6.9  CPSW Ethernet 1 and CPSW Ethernet 2
      10. 2.6.10 GPIO Port Expander
      11. 2.6.11 GPIO Mapping
    7. 2.7  Power
      1. 2.7.1 Power Input
      2. 2.7.2 Power Supply
      3. 2.7.3 Power Sequencing
      4. 2.7.4 AM62D SOC Power
      5. 2.7.5 Current Monitoring
    8. 2.8  Clocking
      1. 2.8.1 Peripheral Ref Clock
    9. 2.9  Reset
    10. 2.10 CPLD Mapping
    11. 2.11 Audio Expansion Connectors (Headers)
      1. 2.11.1 Audio Expansion Connector 1
      2. 2.11.2 Audio Expansion Connector 2
    12. 2.12 Interrupt
    13. 2.13 I2C Address Mapping
  8. 3Hardware Design Files
  9. 4Compliance Information
    1. 4.1 Compliance and Certifications
  10. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
    2. 5.2 Trademarks

2.4.2 Boot modes

The boot mode for the EVM board is defined by two banks of switches SW1 and SW2. This allows for AM62D SoC Boot mode control by either the user (DIP Switch Control).

All the bits of switch (SW1 and SW2) have a weak pull down resistor and a strong pull up resistor as shown in Figure 2-3. Note that OFF setting provides a low logic level (‘0’) and an ON setting provide a high logic level (‘1’).

AUDIO-AM62D-EVM Boot Mode switch (MMCSD Boot) Figure 2-3 Boot Mode switch (MMCSD Boot)

The boot mode pins of the SoC have associated alternate functions during normal operation. Hence isolation is provided using Buffer ICs to cater for alternate pin functionality. The output of the buffer is connected to the boot mode pins on the AM62D SoC and the output is enabled only when the boot mode is needed during a reset cycle.

The input to the buffer is connected to the DIP switch circuit and to the output of an I2C I/O Expander set by the test automation circuit. If the test automation circuit controls the boot mode, all the switches should be manually set to the OFF position. The boot mode buffer is powered by an always ON power supply to ensure that the boot mode remains present even if the SoC is power cycled.

Switch SW1 and SW2 bits [15:0] are used to set the SoC boot mode.

The switch map to the boot mode functions is provided in the following tables.

Table 2-3 BOOTMODE Pin Mapping
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Reserved Reserved Backup Boot Mode Configuration Backup Boot Mode Primary Boot Mode Configuration Primary Boot Mode PLL Configuration
  • BOOTMODE [2:0] – Denote system clock frequency for PLL configuration.
    • Table 2-4 gives details on PLL reference clock selection.
  • BOOTMODE [6:3] – This provides primary boot mode configuration to select the requested boot mode after POR, that is, the peripheral/memory to boot from primary boot device selection details.
    • Table 2-5 gives the primary boot mode configuration details.
  • BOOTMODE [9:7] – These pins provide optional settings and are used in conjunction with the primary boot device selected.
    • Table 2-6 gives primary boot media configuration details.
  • BOOTMODE [12:10] – Select the backup boot mode, that is, the peripheral/memory to boot from, if primary boot device failed.
    • Table 2-7 provides backup boot mode selection details.
  • BOOTMODE [13] – These pins provide optional settings and are used in conjunction with the backup boot device. Switch SW1.6 when ON sets 1 and sets 0 if OFF, see the device-specific TRM.
  • BOOTMODE [15:14] – Reserved. Provides backup boot media configuration options.
Table 2-4 PLL Reference Clock Selection BOOTMODE [2:0]
SW2.3 SW2.2 SW2.1 PLL REF CLK (MHz)
OFF OFF OFF 19.2
OFF OFF ON 20
OFF ON OFF 24
OFF ON ON 25
ON OFF OFF 26
ON OFF ON 27
ON ON OFF RSVD
ON ON ON RSVD
Table 2-5 Boot Device Selection BOOTMODE [6:3]
SW2.7 SW2.6 SW2.5 SW2.4 Primary Boot Device Selected
OFF OFF OFF OFF Serial NAND
OFF OFF OFF ON OSPI
OFF OFF ON OFF QSPI
OFF OFF ON ON SPI
OFF ON OFF OFF Ethernet RGMII
OFF ON OFF ON Ethernet RMII
OFF ON ON OFF I2C
OFF ON ON ON UART
ON OFF OFF OFF MMC/SD card
ON OFF OFF ON eMMC
ON OFF ON OFF USB0
ON OFF ON ON GPMC NAND
ON ON OFF OFF GPMC NOR
ON ON OFF ON Rsvd
ON ON ON OFF xSPI
ON ON ON ON No boot/Dev Boot
Table 2-6 Primary Boot Media Configuration BOOTMODE [9:7]
SW1.2 SW1.1 SW2.8 Boot Device
Reserved Read Mode 2 Read Mode 1 Serial NAND
Reserved Iclk Csel QSPI
Reserved Iclk Csel OSPI
Reserved Mode Csel SPI
Clkout 0 Link Info Ethernet RGMII
Clkout Clk src 0 Ethernet RMII
Bus Reset Reserved Addr I2C
Reserved Reserved Reserved UART
1 Reserved Fs/raw MMC/ SD card
Reserved Reserved Reserved eMMC
Core Volt Mode Lane swap USB0
Reserved Reserved Reserved GPMC NAND
Reserved Reserved Reserved GPMC NOR
Reserved Reserved Reserved Reserved
SFPD Read Cmd Mode xSPI
Reserved ARM/Thumb No/Dev No boot/Dev Boot
Table 2-7 Backup Boot Mode Selection BOOTMODE [12:10]
SW1.5 SW1.4 SW1.3 Backup Boot Device Selected
OFF OFF OFF None(No backup mode)
OFF OFF ON USB
OFF ON OFF Reserved
OFF ON ON UART
ON OFF OFF Ethernet
ON OFF ON MMC/SD
ON ON OFF SPI
ON ON ON I2C