SPRUJG2 December   2024 AM62D-Q1

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   5
  6. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
    4. 1.4 Device Information
    5. 1.5 EVM Revisions and Assembly Variants
  7. 2Hardware
    1. 2.1  Additional Images
    2. 2.2  Key Features
      1. 2.2.1 Processor
      2. 2.2.2 Power Supply
      3. 2.2.3 Memory
      4. 2.2.4 JTAG/Emulator
      5. 2.2.5 Supported Interfaces and Peripherals
      6. 2.2.6 Expansion Connectors/Headers to Support Application Specific Add‐On Boards
    3. 2.3  Power Requirement
    4. 2.4  Setup and Configuration
      1. 2.4.1 EVM DIP Switches
      2. 2.4.2 Boot modes
      3. 2.4.3 User Test LEDs
    5. 2.5  Power ON/OFF Procedures
      1. 2.5.1 Power ON Procedure
      2. 2.5.2 Power OFF Procedure
      3. 2.5.3 Power Test Points
    6. 2.6  Interfaces
      1. 2.6.1  AM62D Audio EVM Interface Mapping
      2. 2.6.2  Audio Interface
        1. 2.6.2.1 Audio Stereo Lineouts
        2. 2.6.2.2 Audio Microphone / Line In
      3. 2.6.3  JTAG Interface
      4. 2.6.4  UART Interface
      5. 2.6.5  USB Interface
        1. 2.6.5.1 USB2.0 Type-A Interface
        2. 2.6.5.2 USB2.0 Type-C Interface
      6. 2.6.6  MCAN Interface
      7. 2.6.7  Memory Interfaces
        1. 2.6.7.1 LPDDR4 Interface
        2. 2.6.7.2 Octal Serial Peripheral Interface (OSPI)
        3. 2.6.7.3 MMC Interfaces
          1. 2.6.7.3.1 MMC0 - eMMC Interface
          2. 2.6.7.3.2 MMC1 - MicroSD Interface
        4. 2.6.7.4 Board ID EEPROM
      8. 2.6.8  Ethernet Interface
      9. 2.6.9  CPSW Ethernet 1 and CPSW Ethernet 2
      10. 2.6.10 GPIO Port Expander
      11. 2.6.11 GPIO Mapping
    7. 2.7  Power
      1. 2.7.1 Power Input
      2. 2.7.2 Power Supply
      3. 2.7.3 Power Sequencing
      4. 2.7.4 AM62D SOC Power
      5. 2.7.5 Current Monitoring
    8. 2.8  Clocking
      1. 2.8.1 Peripheral Ref Clock
    9. 2.9  Reset
    10. 2.10 CPLD Mapping
    11. 2.11 Audio Expansion Connectors (Headers)
      1. 2.11.1 Audio Expansion Connector 1
      2. 2.11.2 Audio Expansion Connector 2
    12. 2.12 Interrupt
    13. 2.13 I2C Address Mapping
  8. 3Hardware Design Files
  9. 4Compliance Information
    1. 4.1 Compliance and Certifications
  10. 5Additional Information
    1. 5.1 Known Hardware or Software Issues
    2. 5.2 Trademarks

2.6.10 GPIO Port Expander

Table 2-14 I/O Expander Signal Details
I/O Expander - 01
Pin no Signal Direction Purpose
P00 GPIO_CPSW2_RST OUTPUT CPSW Ethernet PHY-2 Reset Control GPIO
P01 GPIO_CPSW1_RST OUTPUT CPSW Ethernet PHY-1 Reset Control GPIO
P02 NC -
P03 MMC1_SD_EN OUTPUT SD Card Load Switch Enable
P04 VPP_EN OUTPUT SOC eFuse Voltage(VPP=1.8V) Regulator Enable
P05 GPIO_DIX_RST OUTPUT DIX4192 reset control GPIO
P06 IO_EXP_OPT_EN OUTPUT Optical Buffer Enable
P07 DIX_INT INPUT DIX4192 Interrupt signal
P10 GPIO_eMMC_RSTn OUTPUT eMMC Reset control GPIO
P11 CPLD2_DONE INPUT CPLD2 Programming Indication
P12 CPLD2_INTN INPUT CPLD 2 Interrupt signal
P13 CPLD1_DONE INPUT CPLD1 Programming Indication
P14 CPLD1_INTN INPUT CPLD 1 Interrupt signal
P15 USB_TYPEA_OC_INDICATION INPUT Type A Overcurrent Indication
P16 PCM1_INT INPUT PCM6240 Audio device 1 Interrupt signal
P17 PCM2_INT INPUT PCM6240 Audio device 2 Interrupt signal
P20 GPIO_PCM1_RST OUTPUT PCM6240 Audio device 1 reset control GPIO
P21 TEST_GPIO2 INPUT TEST GPIO2 from Interrupt switch
P22 GPIO_PCM2_RST OUTPUT PCM6240 Audio device 2 reset control GPIO
P23 NC -
P24 IO_MCAN0_STB OUTPUT MCAN 0 STB Control
P25 IO_MCAN1_STB OUTPUT MCAN 1 STB Control
P26 PD_I2C_IRQ INPUT Interrupt Request from PD Controller
P27 IO_EXP_TEST_LED OUTPUT User Test _LED _Enable
Pin no Signal Direction Device
P00 PCM6240_BUF_IO_EN OUTPUT PCM6240 Buffer enable
P01
P02 CPLD1_JTAGENB OUTPUT CPLD 1 JTAG enable
P03 CPLD1_PROGRAMN OUTPUT CPLD 1 Programn Enable
P04 CPLD2_JTAGENB OUTPUT CPLD 2 JTAG enable
P05 CPLD2_PROGRAMN OUTPUT CPLD 2 Programn Enable
P06 NC
P07 NC
P10 CPLD1 TCK OUTPUT CPLD1_JTAG
P11 CPLD1 TMS OUTPUT
P12 CPLD1 TDI OUTPUT
P13 CPLD1 TDO INPUT
P14 CPLD2 TCK OUTPUT CPLD2_JTAG
P15 CPLD2 TMS OUTPUT
P16 CPLD2 TDI OUTPUT
P17 CPLD2 TDO INPUT