SPRZ255F May   2007  – June 2020 TMS320F28044

 

  1.   TMS320F28044 Digital Signal Processor Silicon Revision 0
    1. 1 Introduction
    2. 2 Device and Development Tool Support Nomenclature
    3. 3 Device Markings
    4. 4 Silicon Change Overview
    5. 5 Usage Notes and Known Design Exceptions to Functional Specifications
      1. 5.1 Usage Notes
        1. 5.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 5.2 Known Design Exceptions to Functional Specifications
    6. 6 Documentation Support
  2.   Trademarks
  3.   Revision History

5.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear

Revision(s) Affected: 0

Certain code sequences used for nested interrupts allow the CPU and PIE to enter an inconsistent state that can trigger an unwanted interrupt. The conditions required to enter this state are:

  1. A PIEACK clear is followed immediately by a global interrupt enable (EINT or asm(" CLRC INTM")).
  2. A nested interrupt clears one or more PIEIER bits for its group.

Whether the unwanted interrupt is triggered depends on the configuration and timing of the other interrupts in the system. This is expected to be a rare or nonexistent event in most applications. If it happens, the unwanted interrupt will be the first one in the nested interrupt's PIE group, and will be triggered after the nested interrupt re-enables CPU interrupts (EINT or asm(" CLRC INTM")).

Workaround: Add a NOP between the PIEACK write and the CPU interrupt enable. Example code is shown below.

//Bad interrupt nesting code PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE EINT; //Enable nesting in the CPU //Good interrupt nesting code PieCtrlRegs.PIEACK.all = 0xFFFF; //Enable nesting in the PIE asm(" NOP"); //Wait for PIEACK to exit the pipeline EINT; //Enable nesting in the CPU