SPRZ423K October   2014  – May 2024 TMS320F28075 , TMS320F28075-Q1 , TMS320F28076

 

  1.   1
  2.   Abstract
  3. 1Usage Notes and Advisories Matrices
    1. 1.1 Usage Notes Matrix
    2. 1.2 Advisories Matrix
  4. 2Nomenclature, Package Symbolization, and Revision Identification
    1. 2.1 Device and Development Support Tool Nomenclature
    2. 2.2 Devices Supported
    3. 2.3 Package Symbolization and Revision Identification
  5. 3Silicon Revision C Usage Notes and Advisories
    1. 3.1 Silicon Revision C Usage Notes
      1. 3.1.1 PIE: Spurious Nested Interrupt After Back-to-Back PIEACK Write and Manual CPU Interrupt Mask Clear
      2. 3.1.2 Caution While Using Nested Interrupts
      3. 3.1.3 SYS/BIOS: Version Implemented in Device ROM is not Maintained
      4. 3.1.4 SDFM: Use Caution While Using SDFM Under Noisy Conditions
      5. 3.1.5 McBSP: XRDY Bit can Hold the Not-Ready Status (0) if New Data is Written to the DX1 Register Without Verifying if the XRDY Bit is in its Ready State (1)
    2. 3.2 Silicon Revision C Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
      10.      Advisory
      11.      Advisory
      12.      Advisory
      13.      Advisory
      14.      Advisory
      15.      Advisory
      16.      Advisory
      17.      Advisory
      18.      Advisory
      19.      Advisory
      20.      Advisory
      21.      Advisory
      22.      Advisory
      23.      Advisory
      24.      Advisory
      25.      Advisory
      26.      Advisory
      27.      Advisory
      28.      Advisory
      29.      Advisory
      30.      Advisory
      31.      Advisory
      32.      Advisory
      33.      Advisory
      34.      Advisory
      35.      Advisory
      36.      Advisory
  6. 4Silicon Revision B Usage Notes and Advisories
    1. 4.1 Silicon Revision B Usage Notes
    2. 4.2 Silicon Revision B Advisories
      1.      Advisory
      2.      Advisory
      3.      Advisory
      4.      Advisory
      5.      Advisory
      6.      Advisory
      7.      Advisory
      8.      Advisory
      9.      Advisory
  7. 5Documentation Support
  8. 6Trademarks
  9. 7Revision History

Advisory

Low-Power Modes: Power Down Flash or Maintain Minimum Device Activity

Revisions Affected

B, C

Details

The device has an intentional current path from VDD3VFL (flash supply) to VDD. Since the HALT, STANDBY, IDLE, or other low-activity device conditions can have low current demand on VDD, this VDD3VFL current can cause VDD to rise above the recommended operating voltage.

There will be zero current load to the external system VDD regulator while in this condition. This is not an issue for most regulators; however, some system voltage regulators require a minimum load for proper operation.

Workarounds

Workaround 1: Power down the flash before entering HALT, STANDBY, IDLE, or other low-activity device conditions. This will disable the internal current path. This workaround must be executed from RAM.

            
       EALLOW;
       // power down bank
       Flash0CtrlRegs.FBFALLBACK.bit.BNKPWR0 = 0;
       asm(" RPT #8 || NOP");
       // power down pump
       Flash0CtrlRegs.FPAC1.bit.PMPPWR = 0;
       asm(" RPT #8 || NOP");
       EDIS; 
       // enter low power mode
       asm(" IDLE");

Workaround 2: Keep SYSCLK at a minimum of 100 MHz during STANDBY or IDLE. This activity will be sufficient to consume the internal current.

Workaround 3: An external 82-Ω resistor can be added to the board between VDD and VSS.