SPRZ426F November 2014 – September 2024 DRA710 , DRA712 , DRA714 , DRA716 , DRA718 , DRA722 , DRA724 , DRA725 , DRA726
DSS VOUT1 and VOUT3 Reduced Fequency. All VOUTn Should Use SLOW Slew
High
The maximum frequency of operation for VOUT1 and VOUT3 is reduced when operating in 3.3V mode; and all VOUT interfaces (VOUT1/VOUT2/VOUT3) must be programmed to operate in SLOW slew mode in all cases.
When the VOUT1/VOUT3 interfaces are used in 3.3V mode of operation at higher frequencies there can be excessive overshoot/undershoot on the IOs when the interface data bus switches concurrently. This can impact the long term reliability of these IOs.
When the VOUT1/VOUT2/VOUT3 interfaces are operated in FAST slew mode (regardless of frequency) there can be excessive overshoot/undershoot on the IOs when the interface data bus switches concurrently. This can impact the long term reliability of these IOs.
VOUT1/VOUT3 in 3.3V mode should be limited to a maximum of 75 MHz. Maximum frequency is supported in 1.8V mode.
Software should set the VOUT1/VOUT2/VOUT3 Pad Configuration Register SLEWCONTROL bitfield to SLOW Slew setting.
Note this must be considered in the pin mux programming and VDDSHVx supply connections.
DRA72x SR 2.0, 1.0
TDA2Ex (23mm): 2.0, 1.0
AM571x: 2.1, 2.0, 1.0
DRA72x: 2.0, 1.0