CRITICALITY

Low

DESCRIPTION

Internal to the MMC module, a second stage latch is used to recapture data captured by DLL delayed clock, mmci_dll_clk. The second stage latch captures with the original transmitting clock, mmci_clk.

Figure 2-1 Simplified SoC 192-MHz Mode DLL Block Diagram

mmci_dll_clk and mmci_clk both run at the same clock frequency. This results in a narrow range of tuning ratio elements, where the delayed mmci_dll_clk comes in phase with mmci_clk. If the clocks are in phase, the data captured by the first clock violates the setup and hold time requirements needed for the second stage latch, resulting in incorrectly read data. This is known as tuning re-timing errors.

For systems in which MMC DLL tuning algorithm* chooses a ratio less than 40, which is sufficiently far from the lowest re-timing error ratio element, no workaround is necessary.

WORKAROUND

A DLL tuning algorithm has been implemented that can avoid the tuning re-timing errors. More details on this can be found in App Note SPRACA9. The following notes summarize the updated algorithm:

1. Implement two stage tuning. The software begins with the regular tuning algorithm, using 4-step increments, to optimize boot time. When the initial ratio is chosen within the largest passing window, the software checks 10 tuning steps in each direction, using single steps, to identify whether the chosen ratio is at risk of a tuning re-timing error. If at risk, the value of the chosen ratio is adjusted to move away from the error. If not, the chosen ratio is used unchanged.
2. Choose ratio based on temperature. Both tuning band errors and tuning re-timing errors shift with temperature. The software takes this dependency into consideration when selecting the tuning ratio element to use for functionality.

REVISIONS IMPACTED

DRA72x SR 2.0, 1.0
DRA71x SR 2.1, 2.0

DRA79x: 2.1, 2.0

TDA2Ex (23mm): 2.0, 1.0

TDA2Ex (17mm): 2.1, 2.0

AM571x: 2.1, 2.0, 1.0

AM570x: 2.1, 2.0

DRA72x: 2.0, 1.0

DRA71x: 2.1, 2.0