CRITICALITY

Low

DESCRIPTION

If the DCAN module is allowed to enter/exit clock-gated mode dynamically while traffic is present on the DCAN interface (even if the traffic is not to/from the SoC) then the DCAN module and PRCM handshake state machines can become out of sync resulting in the DCAN module hanging.

WORKAROUND

In order to cleanly initialize the DCAN module the following sequence should be followed. Steps 1 and 2 can happen in any order, but should occur before Step 3.

1. Configure the DCAN module’s clock domain in SW_WKUP mode
   • DCAN1: CM_WKUPAON_CLKSTCTRL. CLKTRCTRL = 0x2
   • DCAN2: CM_L4PER2_CLKSTCTRL. CLKTRCTRL= 0x2
2. Configure CD_L4_CFG for NO_SLEEP mode
   • CM_L4CFG_CLKSTCTRL. CLKTRCTRL = 0x0
3. Execute RAM Init Sequence:
   • Mask the RX input via pinmux configuration
     • Select default/gpio function instead of dcan rx. Specific register and MUXMODE value depends on pin-mux used on the board
     • For DCAN1 muxed with WAKEUP0: CTRL_CORE_PAD_WAKEUP0.MUXMODE = 0xF
   • Enable DCAN module
     • DCAN1: CM_WKUPAON_DCAN1_CLKCTRL.MODULEMODE = 0x2
     • DCAN2: CM_L4PER2_DCAN2_CLKCTRL.MODULEMODE = 0x2
   • Perform RAM_INIT sequence
     • DCAN1: CTRL_CORE_CONTROL_IO_2. DCAN1_RAMINIT_START = 0x1
     • DCAN2: CTRL_CORE_CONTROL_IO_2. DCAN2_RAMINIT_START = 0x1
     • Poll for CTRL_CORE_CONTROL_IO_2. DCAN1_RAMINIT_DONE and DCAN2_RAMINIT_DONNE
   • Enable RX input via pin mux configuration
     • Select dcan_rx function
     • Specific register and MUXMODE value depends on pin-mux used on the board
     • For DCAN1 muxed with WAKEUP0: CTRL_CORE_PAD_WAKEUP0.MUXMODE = 0x1

REVISIONS IMPACTED

DRA72x SR 2.0, 1.0
DRA71x SR 2.1, 2.0

DRA79x: 2.1, 2.0

TDA2Ex (23mm): 2.0, 1.0

TDA2Ex (17mm): 2.1, 2.0

AM571x: 2.1, 2.0, 1.0

AM570x: 2.1, 2.0

DRA72x: 2.0, 1.0

DRA71x: 2.1, 2.0