SPRZ429N July   2014  – July 2024 AM5726 , AM5728 , AM5729

 

  1.   1
  2. 1Introduction
    1.     Related Documentation
    2.     Trademarks
    3.     Modules Impacted
  3. 2Silicon Advisories
    1.     Revisions SR 2.0, 1.1 - Advisories List
    2.     i202
    3.     i378
    4.     i631
    5.     i694
    6.     i698
    7.     i699
    8.     i727
    9.     i729
    10.     i734
    11.     i767
    12.     i782
    13.     i783
    14.     i802
    15.     i803
    16.     i807
    17.     i808
    18.     i809
    19.     i810
    20.     i813
    21.     i814
    22.     i815
    23.     i818
    24.     i819
    25.     i820
    26.     i824
    27.     i826
    28.     i829
    29.     i834
    30.     i837
    31.     i840
    32.     i841
    33.     i842
    34.     i843
    35.     i847
    36.     i849
    37.     i852
    38.     i854
    39.     i855
    40.     i856
    41.     i859
    42.     i861
    43.     i862
    44.     i863
    45.     i868
    46.     i869
    47.     i870
    48.     i871
    49.     i872
    50.     i874
    51.     i875
    52.     i878
    53.     i879
    54.     i880
    55.     i882
    56.     i883
    57.     i884
    58.     i887
    59.     i889
    60.     i890
    61.     i893
    62.     i895
    63.     i896
    64.     i897
    65.     i898
    66.     i899
    67.     i900
    68.     i901
    69.     i903
    70.     i916
    71.     i927
    72.     i929
    73.     i930
    74.     i932
    75.     i933
    76.     i936
    77.     i940
    78.     i2446
  4. 3Silicon Limitations
    1.     Revisions SR 2.0, 1.1 - Limitations List
    2.     i596
    3.     i641
    4.     i833
    5.     i838
    6.     i845
    7.     i848
    8.     i850
    9.     i851
    10.     i853
    11.     i857
    12.     i858
    13.     i876
    14.     i877
    15.     i892
    16.     i909
    17.     i922
    18.     i925
  5. 4Silicon Cautions
    1.     Revisions SR 2.0, 1.1 - Cautions List
    2. 4.1 106
    3.     i827
    4.     i832
    5.     i836
    6.     i839
    7.     i864
    8.     i885
    9.     i886
    10.     i912
    11.     i926
    12.     i931
    13.     i935
  6. 5Revision History

i935

MSI Bit in PCIECTRL_TI_CONF_IRQSTATUS_MSI Register Does Not Clear Automatically

CRITICALITY

Low

DESCRIPTION

The MSI bit in PCIECTRL_TI_CONF_IRQSTATUS_MSI register does not clear automatically even after all the vectors in PCIECTRL_PL_MSI_CTRL_INT_STATUS_N registers are cleared.

GUIDELINES

Software should manually clear PCIECTRL_TI_CONF_IRQSTATUS_MSI[4] MSI bit after making sure there are no vectors set in PCIECTRL_PL_MSI_CTRL_INT_STATUS_N registers. If MSI bit is cleared with some of the bits of PCIECTRL_PL_MSI_CTRL_INT_STATUS_N still set then those interrupts may be lost which may lead to non-functional remote endpoints.

Following is the recommended sequence for handling MSI interrupt to avoid missing any MSI interrupts:

  1. Software reads PCIECTRL_TI_CONF_IRQSTATUS_MSI status register, and identifies an (unspecified) MSI event, as opposed to a PCI legacy event.
  2. Software clears PCIECTRL_TI_CONF_IRQSTATUS_MSI[4] MSI.
  3. Software reads PCIECTRL_PL_MSI_CTRL_INT_STATUS_N and identifies EP functions that raised MSI.
  4. Software clears PCIECTRL_PL_MSI_CTRL_INT_STATUS_N status bit.
  5. Software calls the EP function specific interrupt handlers for each of the vectors.
  6. Repeat steps 3 to 5 until PCIECTRL_PL_MSI_CTRL_INT_STATUS_N reads 0.
  7. Exit MSI IRQ handler, only if PCIECTRL_PL_MSI_CTRL_INT_STATUS_N is 0

REVISIONS IMPACTED

SR 2.0, 1.1

TDA2x: 2.0, 1.1, 1.0

DRA75x, DRA74x: 2.0, 1.1, 1.0

AM572x: 2.0, 1.1