SPRZ447E July   2017  – July 2024 AM5746 , AM5748 , AM5749

 

  1.   1
  2. 1Introduction
    1.     Related Documentation
    2.     Trademarks
    3.     Modules Impacted
  3. 2Silicon Advisories
    1.     Revisions SR 1.0 - Advisories List
    2.     i202
    3.     i378
    4.     i631
    5.     i694
    6.     i698
    7.     i699
    8.     i709
    9.     i727
    10.     i729
    11.     i734
    12.     i767
    13.     i782
    14.     i783
    15.     i802
    16.     i803
    17.     i807
    18.     i808
    19.     i809
    20.     i810
    21.     i813
    22.     i814
    23.     i815
    24.     i818
    25.     i819
    26.     i820
    27.     i824
    28.     i826
    29.     i829
    30.     i834
    31.     i849
    32.     i856
    33.     i862
    34.     i863
    35.     i869
    36.     i870
    37.     i871
    38.     i872
    39.     i874
    40.     i878
    41.     i879
    42.     i883
    43.     i889
    44.     i890
    45.     i893
    46.     i896
    47.     i897
    48.     i898
    49.     i899
    50.     i900
    51.     i903
    52.     i904
    53.     i916
    54.     i929
    55.     i930
    56.     i932
    57.     i933
    58.     i936
    59.     i940
    60.     i2446
  4. 3Silicon Limitations
    1.     Revisions SR 1.0 - Limitations List
    2.     i596
    3.     i641
    4.     i833
    5.     i838
    6.     i845
    7.     i848
    8.     i876
    9.     i877
    10.     i892
    11.     i909
    12.     i925
  5. 4Silicon Cautions
    1.     Revisions SR 1.0 - Cautions List
    2.     i827
    3.     i832
    4.     i836
    5.     i839
    6.     i864
    7.     i885
    8.     i886
    9.     i912
    10.     i926
    11.     i931
    12.     i935
    13.     i937
  6. 5Revision History

i929

MMC1/2 SDR104/HS200 Mode DLL Delay Value May Result In Unexpected Tuning Pattern Errors

CRITICALITY

Low

DESCRIPTION

Internal to the MMC module, a second stage latch is used to recapture data captured by DLL delayed clock, mmci_dll_clk. The second stage latch captures with the original transmitting clock, mmci_clk.

 Simplified SoC 192-MHz Mode DLL Block DiagramFigure 2-1 Simplified SoC 192-MHz Mode DLL Block Diagram

mmci_dll_clk and mmci_clk both run at the same clock frequency. This results in a narrow range of tuning ratio elements, where the delayed mmci_dll_clk comes in phase with mmci_clk. If the clocks are in phase, the data captured by the first clock violates the setup and hold time requirements needed for the second stage latch, resulting in incorrectly read data. This is known as tuning re-timing errors.

For systems in which MMC DLL tuning algorithm* chooses a ratio less than 40, which is sufficiently far from the lowest re-timing error ratio element, no workaround is necessary.

WORKAROUND

A DLL tuning algorithm has been implemented that can avoid the tuning re-timing errors. More details on this can be found in App Note SPRACA9. The following notes summarize the updated algorithm:

  1. Implement two stage tuning. The software begins with the regular tuning algorithm, using 4-step increments, to optimize boot time. When the initial ratio is chosen within the largest passing window, the software checks 10 tuning steps in each direction, using single steps, to identify whether the chosen ratio is at risk of a tuning re-timing error. If at risk, the value of the chosen ratio is adjusted to move away from the error. If not, the chosen ratio is used unchanged.
  2. Choose ratio based on temperature. Both tuning band errors and tuning re-timing errors shift with temperature. The software takes this dependency into consideration when selecting the tuning ratio element to use for functionality.

Note: NOTE: *Legacy MMC DLL tuning algorithm are algorithms that were implemented before errata i929 was published. These algorithms do not take temperature nor single step tuning into consideration and were only tuned with step size = 4.

REVISIONS IMPACTED

AM574x SR 1.0
AM576x SR 1.0

AM574x: 1.0

DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0

TDA2Px: 1.0

AM576x: 1.0