SPRZ447E July   2017  – July 2024 AM5746 , AM5748 , AM5749

 

  1.   1
  2. 1Introduction
    1.     Related Documentation
    2.     Trademarks
    3.     Modules Impacted
  3. 2Silicon Advisories
    1.     Revisions SR 1.0 - Advisories List
    2.     i202
    3.     i378
    4.     i631
    5.     i694
    6.     i698
    7.     i699
    8.     i709
    9.     i727
    10.     i729
    11.     i734
    12.     i767
    13.     i782
    14.     i783
    15.     i802
    16.     i803
    17.     i807
    18.     i808
    19.     i809
    20.     i810
    21.     i813
    22.     i814
    23.     i815
    24.     i818
    25.     i819
    26.     i820
    27.     i824
    28.     i826
    29.     i829
    30.     i834
    31.     i849
    32.     i856
    33.     i862
    34.     i863
    35.     i869
    36.     i870
    37.     i871
    38.     i872
    39.     i874
    40.     i878
    41.     i879
    42.     i883
    43.     i889
    44.     i890
    45.     i893
    46.     i896
    47.     i897
    48.     i898
    49.     i899
    50.     i900
    51.     i903
    52.     i904
    53.     i916
    54.     i929
    55.     i930
    56.     i932
    57.     i933
    58.     i936
    59.     i940
    60.     i2446
  4. 3Silicon Limitations
    1.     Revisions SR 1.0 - Limitations List
    2.     i596
    3.     i641
    4.     i833
    5.     i838
    6.     i845
    7.     i848
    8.     i876
    9.     i877
    10.     i892
    11.     i909
    12.     i925
  5. 4Silicon Cautions
    1.     Revisions SR 1.0 - Cautions List
    2.     i827
    3.     i832
    4.     i836
    5.     i839
    6.     i864
    7.     i885
    8.     i886
    9.     i912
    10.     i926
    11.     i931
    12.     i935
    13.     i937
  6. 5Revision History

i783

SATA Lockup after SATA DPLL Unlock/Relock

CRITICALITY

Low

DESCRIPTION

Consider the following scenario:

  1. Initialize SATA.
  2. Enable TX/RX PHYs, start controller DMA engine, spin up the device (SATA_PxCMD[1] SUD = 0x1).
  3. Enable aggressive transitions to partial or slumber: SATA_PxCMD[26] and ALPE = 0x1 and SATA_PxCMD[27] = 0x0/0x1
  4. Perform DMA/PIO transfers.
  5. Wait until all commands are finished. Interface (only physical lines) should go to low power mode.
  6. Check that transition to partial is complete.
  7. Stop all DMA machines, set SATA_PxCMD[1] SUD bit to 0, power down the PHYs.
  8. Unlock SATA DPLL (DPLLCTRL_SATA.PLL_GO[0] PLL_GO = 0x0)
  9. Relock SATA DPLL (DPLLCTRL_SATA.PLL_GO[0] PLL_GO = 0x1), go out to low power mode.
  10. Go to Step 2.

After the first loop, when re-executing Step 2 and spinning up the device, communication is blocked between the host and the device, and the SATA is locked up.

A simpler scenario can be used to reproduce the issue. In this case, no SATA commands are issued by the host.

  1. Initialize the SATA.
  2. Enable PHYs, start RX DMA engine, initiate staggered spin-up, and start TX DMA engine.
  3. Read SATA status register SATA_PxTFD.
  4. Stop all DMA engine, set SATA_PxCMD[1] SUD bit to 0, power down the PHYs.
  5. Unlock and relock SATA DPLL(DPLLCTRL_SATA.PLL_GO[0] PLL_GO = 0x0 then DPLLCTRL_SATA.PLL_GO[0] PLL_GO = 0x1).
  6. Go to Step 2.

These issues are usually encountered immediately after the first loop, although this is not always the case.

WORKAROUND

To prevent the SATA Lockup the SATA DPLL Unlock sequence must be performed as follows:

  1. Unlock SATA DPLL (SATA DPLL(DPLLCTRL_SATA.PLL_GO[0] PLL_GO = 0x0)
  2. Toggle SATA_PLL_SOFT_RESET bit of CTRL_CORE_SMA_SW_0 register from 0->1
  3. Toggle SATA_PLL_SOFT_RESET bit of CTRL_CORE_SMA_SW_0 register from 1->0

REVISIONS IMPACTED

AM574x SR 1.0
AM576x SR 1.0

AM574x: 1.0

DRA75xP, DRA74xP, DRA77xP, DRA76xP: 1.0

TDA2Px: 1.0

AM576x: 1.0