SPRZ452I july 2018 – may 2023 AM6526 , AM6528 , AM6546 , AM6548
PCIe: Root Port does not set the Link Bandwidth Management and Link Autonomous Bandwidth status bits
PCIe defines two status fields called ‘Link Bandwidth Management’ and ‘Link Autonomous Bandwidth’ as part of the ‘Link Status Register’ for Downstream port. Hardware is expected to set one of these status fields when a link speed change event occurs depending on the reason for this change.
These status bits may not be set even for a valid link speed change. This can happen if the PHY communicates the link speed change event to MAC after a high delay (> 800ns).
As a result of this issue, software may not be able to differentiate between autonomous link speed change, directed link speed change through ‘Retrain Link’ field in 'Link Control Register', or speed change due to unreliable link.
This issue only applies to Root Complex mode.
None. Software can periodically read the ‘Current Link Speed’ field in ‘Link Status Register’ to detect link speed change. But, there is no workaround to obtain additional information on whether link speed change was autonomous, directed or due to unreliable link.