Revision(s) Affected:

AM65x SR 1.0

Details:

Snoop filter can be invalidated when different system masters access the same memory location with different coherency attributes. The MSMC snoop filter retains knowledge of memory cached locally by master (for example, Arm Cortex®-A53 local cache). A coherent transaction performed by another system master through the MSMC will check the snoop filter and ensure the locally-cached data is accessed for transaction, and that the memory and cache is kept coherent. If, however, a non-coherent transaction is performed by another master through MSMC, it will invalidate the snoop filter entry for the locally-cached data and future transactions will not perform a snoop on the cached contents and the memory and cache are no longer coherent.

Workaround(s):

The workaround to avoid this scenario is to control the accesses to cacheable memory. During software initialization (for example, exception level startup) on different A53 clusters, the cache view to memory needs to be controlled such that it is consistent between clusters. When one cluster is performing a non-coherent access to memory, software on the other cluster must ensure that it does not have the memory location in its local cache. This applies to any SoC device variants where there are two A53 clusters in the SoC.

For IO transactions with DMA, it is required that all DMA masters perform coherent transactions only to any memory that is cached locally by an A53 core, unless it is accessing a globally non-coherent memory space. This applies to all SoC device variants, irrespective of the number of A53 clusters in the SoC.