SPRZ452I july 2018 – may 2023 AM6526 , AM6528 , AM6546 , AM6548
DDR: Controller can violate timing from Self-Refresh Exit (SRX) to Power-Down Entry (PDE) for DDR3
The DDR3 JEDEC specification states: "CKE must remain HIGH for the entire Self-Refresh exit period (tXSDLL) for proper operation except for Self-Refresh re-entry". However, if a Power-Down Entry (PDE) is requested immediately after a Self-Refresh Exit (SRX), the controller can issue the PDE command tXS time after the SRX command, and thereby violating the DDR3 JEDEC specification.
Set DRAMTMG8.t_xs_x32 = DRAMTMG8.t_xs_dll_x32.Please note that this will result in increased timing for commands that do not require a locked DLL from self-refresh exit, i.e., commands other than reads.