Details:

PTM Master Time is calculated by the Requester using the round trip time for PTM request and response (Requester to Responder and back). If the calculated round trip time is negative, it causes the Requester local clock to have a huge offset of 2^63 nanoseconds.

The following is the equation used to calculate PTM Master Time (same as PTM Requester local clock):

PTM Master Time at t1’ = t2’ – round_trip/2

Where round_trip = ((t4-t1) – (t3-t2))

Please note that t1 is the estimated time for PTM Request at the Requester’s upstream port. This includes the local time added with the programmed MAC and PHY latencies for transmit. Similarly t4 is the estimated time for PTM Response and the Requester’s upstream port. This includes local time subtracted by the programmed MAC and PHY latencies for receive.

PTM Master Time calculated after receiving ResponseD message is then used to update the Requester’s local clock.

Round trip time can become negative if (t3-t2) is greater than (t4-t1). This can happen if either or both of below scenarios happen:

1. PTM Requester’s transmit and receive latency registers are programmed with values that are close to or greater than actual PHY and MAC latency.

2. The clock frequencies between Requester’s Upstream port and Responder’s Downstream port have significant difference and the actual wire delays between these two ports are short (few nanoseconds).

The issue arises because the round trip time is stored as an unsigned number and is right shifted to create the divide by two value. As a result, round_trip/2 component in the PTM Master Time equation becomes a very large positive number. This leads to the following issues:

1. 2^63 nanoseconds offset in the adjusted Requester’s local clock going to CPTS for hardware push.

2. The VSEC PTM registers have this offset as well. The affected PTM registers are PCIE_EP_PTM_REQ_LOCAL_LSB_OFF, PCIE_EP_PTM_REQ_LOCAL_MSB_OFF, PCIE_EP_PTM_REQ_T1_LSB_OFF, PCIE_EP_PTM_REQ_T1_MSB_OFF, PCIE_EP_PTM_REQ_T1P_LSB_OFF, PCIE_EP_PTM_REQ_T1P_MSB_OFF, PCIE_EP_PTM_REQ_T4_LSB_OFF, PCIE_EP_PTM_REQ_T4_MSB_OFF, PCIE_EP_PTM_REQ_T4P_LSB_OFF, PCIE_EP_PTM_REQ_T4P_MSB_OFF.

Workaround(s):

One of the following workarounds have to be implemented:

1. Program the transmit latency (PCIE_EP_PTM_REQ_TX_LATENCY_OFF register) and receive latency (PCIE_EP_PTM_REQ_RX_LATENCY_OFF) to zero. This will eliminate the issue as long as clock drift between Requester/EP and Responder/RC is less than 4100pm. However, this workaround will increase the deviation for Requester clock with respect to Responder’s PTM Master Time.

2. Detect and correct for this 2^63 nanoseconds offset: -

• Ignore bits 63 and 62 of the local clock and timestamps in VSEC PTM register space.
• Do not set PTM_CLK_SEL field in PTMCFG register to values of 62 or 63. This will prevent the CPTS hardware push logic from using the two most significant bits of the PTM local clock. This limits maximum PTM time to less than 136 years.