SPRZ452I july 2018 – may 2023 AM6526 , AM6528 , AM6546 , AM6548
PCIE: Compliance test fails with certain lane reversal and lane polarity inversion conditions when using Enter Compliance bit
Compliance test fails because modified Compliance Pattern is not detected in the following cases when compliance is entered using Enter Compliance bit in Link Control 2 register:
1. Using 8b/10b encoding (2.5 GT/s and 5 GT/s) and lane is polarity inverted.
2. Using 128b/130b encoding (8 GT/s) and lane is both polarity inverted and reversed (negotiated during previous link training).
Do not use Enter Compliance bit in Link Control 2 register for forcing entry to Compliance state if this issue applies (based on lane reversal and polarity inversion combinations). Instead, compliance entry has to be initiated using Compliance Receive bit in training sequence packets.