Details:

Controller derating logic samples Mode Register 4 (MR4) of the LPDDR4 only if MR4[7], the Temperature Update Flag (TUF) is equal to 1. However, if the system is hot or cold prior to DERATEEN.derate_enable = 1, then there is no guarantee that MR4[7] = 1 will be set even though the MR4[2:0] != 3'b011 (not 1x tREFI case).

As the logic does not sample MR4[2:0] correctly it can result in incorrect refresh period being used, or incorrect derated timing parameters (tRCD, tRAS, tRP, tRRD) being used. This can result in to functional impact in normal operation such as protocol violation leading to potentially unexpected behavior of the memory system and/or possible data loss/corruption in SDRAM.

Workaround(s):

When enabling controller derating logic:1. Set DERATEEN.derate_enable = 12. Perform a read of MR4 register via software registers MRCTRL*/MRSTAT3. If MR4[7] = 0 and MR4[2:0] = 3'b011, then it is safe to use controller derating logic, otherwise set DERATEEN.derate_enable=0 and temperature derating should be performed via software.

1. Set DERATEEN.derate_enable = 1
2. Perform a read of MR4 register via software registers MRCTRL*/MRSTAT
3. If MR4[7] = 0 and MR4[2:0] = 3'b011, then it is safe to use controller derating logic, otherwise set DERATEEN.derate_enable=0 and temperature derating should be performed via software.